From patchwork Wed Feb 3 12:02:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 577880 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id F12361402C4 for ; Wed, 3 Feb 2016 23:03:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755528AbcBCMDh (ORCPT ); Wed, 3 Feb 2016 07:03:37 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:7812 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753257AbcBCMDf (ORCPT ); Wed, 3 Feb 2016 07:03:35 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 696A8CB743F13; Wed, 3 Feb 2016 12:03:32 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 3 Feb 2016 12:03:34 +0000 Received: from localhost (10.100.200.105) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 3 Feb 2016 12:03:33 +0000 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , , Subject: [PATCH v2 2/6] net: pch_gbe: Mark Minnow PHY reset GPIO active low Date: Wed, 3 Feb 2016 12:02:40 +0000 Message-ID: <1454500964-6256-3-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454500964-6256-1-git-send-email-paul.burton@imgtec.com> References: <1454500964-6256-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.105] Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The Minnow PHY reset GPIO is set to 0 to enter reset & 1 to leave reset - that is, it is an active low GPIO. In order to allow for the code to be made more generic by further patches, indicate to the GPIO subsystem that the GPIO is active low & invert the values it is set to such that they reflect logically whether the device is being reset or not. Signed-off-by: Paul Burton --- Changes in v2: None drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c index 3b98b263b..fde4c11 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c @@ -2717,7 +2717,8 @@ err_free_netdev: */ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev) { - unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT; + unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW | + GPIOF_EXPORT | GPIOF_ACTIVE_LOW; unsigned gpio = MINNOW_PHY_RESET_GPIO; int ret; @@ -2729,10 +2730,10 @@ static int pch_gbe_minnow_platform_init(struct pci_dev *pdev) return ret; } - gpio_set_value(gpio, 0); - usleep_range(1250, 1500); gpio_set_value(gpio, 1); usleep_range(1250, 1500); + gpio_set_value(gpio, 0); + usleep_range(1250, 1500); return ret; }