From patchwork Wed Jan 20 09:20:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 570602 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2B51C1400CB for ; Wed, 20 Jan 2016 20:26:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758399AbcATJ0R (ORCPT ); Wed, 20 Jan 2016 04:26:17 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:26790 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758239AbcATJY6 (ORCPT ); Wed, 20 Jan 2016 04:24:58 -0500 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id u0K9JwT8025476; Wed, 20 Jan 2016 01:24:13 -0800 Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 20j4408gxf-1 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Jan 2016 01:24:13 -0800 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Wed, 20 Jan 2016 01:24:12 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server id 15.0.1104.5 via Frontend Transport; Wed, 20 Jan 2016 01:24:12 -0800 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id 989663F703F; Wed, 20 Jan 2016 01:24:10 -0800 (PST) From: Jisheng Zhang To: , , , , , , , CC: , , , , , Jisheng Zhang Subject: [PATCH v2 3/4] net: mvneta: get optional axi clk Date: Wed, 20 Jan 2016 17:20:21 +0800 Message-ID: <1453281622-7829-4-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1453281622-7829-1-git-send-email-jszhang@marvell.com> References: <1453281622-7829-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-01-20_04:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310008 definitions=main-1601200165 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Some platforms may provide more than one clk for the mvneta IP, for example Marvell BG4CT provides "core" clk for the mac core, and "axi" clk for the AXI bus logic. Obviously this "axi" clk also need to be enabled. This patch adds this optional "axi" clk support. Signed-off-by: Jisheng Zhang --- drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 736a9ec..ca25933 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -373,6 +373,8 @@ struct mvneta_port { /* Core clock */ struct clk *clk; + /* AXI clock */ + struct clk *clk_axi; u8 mcast_count[256]; u16 tx_ring_size; u16 rx_ring_size; @@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev) clk_prepare_enable(pp->clk); + pp->clk_axi = devm_clk_get(&pdev->dev, "axi"); + if (!IS_ERR(pp->clk_axi)) + clk_prepare_enable(pp->clk_axi); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pp->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pp->base)) { @@ -3726,6 +3732,7 @@ err_free_stats: err_free_ports: free_percpu(pp->ports); err_clk: + clk_disable_unprepare(pp->clk_axi); clk_disable_unprepare(pp->clk); err_put_phy_node: of_node_put(phy_node); @@ -3743,6 +3750,7 @@ static int mvneta_remove(struct platform_device *pdev) struct mvneta_port *pp = netdev_priv(dev); unregister_netdev(dev); + clk_disable_unprepare(pp->clk_axi); clk_disable_unprepare(pp->clk); free_percpu(pp->ports); free_percpu(pp->stats);