@@ -373,6 +373,8 @@ struct mvneta_port {
/* Core clock */
struct clk *clk;
+ /* AXI clock */
+ struct clk *clk_axi;
u8 mcast_count[256];
u16 tx_ring_size;
u16 rx_ring_size;
@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)
clk_prepare_enable(pp->clk);
+ pp->clk_axi = devm_clk_get(&pdev->dev, "axi");
+ if (!IS_ERR(pp->clk_axi))
+ clk_prepare_enable(pp->clk_axi);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pp->base)) {
@@ -3726,6 +3732,7 @@ err_free_stats:
err_free_ports:
free_percpu(pp->ports);
err_clk:
+ clk_disable_unprepare(pp->clk_axi);
clk_disable_unprepare(pp->clk);
err_put_phy_node:
of_node_put(phy_node);
@@ -3743,6 +3750,7 @@ static int mvneta_remove(struct platform_device *pdev)
struct mvneta_port *pp = netdev_priv(dev);
unregister_netdev(dev);
+ clk_disable_unprepare(pp->clk_axi);
clk_disable_unprepare(pp->clk);
free_percpu(pp->ports);
free_percpu(pp->stats);
Some platforms may provide more than one clk for the mvneta IP, for example Marvell BG4CT provides "core" clk for the mac core, and "axi" clk for the AXI bus logic. Obviously this "axi" clk also need to be enabled. This patch adds this optional "axi" clk support. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++ 1 file changed, 8 insertions(+)