From patchwork Mon Nov 30 22:24:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Shi X-Patchwork-Id: 550539 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E4920140180 for ; Tue, 1 Dec 2015 09:43:56 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro-org.20150623.gappssmtp.com header.i=@linaro-org.20150623.gappssmtp.com header.b=CF1GSqXF; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755043AbbK3Wnl (ORCPT ); Mon, 30 Nov 2015 17:43:41 -0500 Received: from mail-pa0-f51.google.com ([209.85.220.51]:35356 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753968AbbK3Wnk (ORCPT ); Mon, 30 Nov 2015 17:43:40 -0500 Received: by pacej9 with SMTP id ej9so198604642pac.2 for ; Mon, 30 Nov 2015 14:43:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=5RCiLAeWSJzTzCoAPJIp4ghv9LaxaNUxgZhZVJHMMMw=; b=CF1GSqXFhC/dUlqDtaQL9dxQr/Qi6bmKlHBnZOJXEPkirSDwrtvnLO8KNSfCkiuLM2 W31llgoFQiKv+Hnz6W0xgFHLiDzQ2QrTus6YruhcbIaFlJObyRm1zEaqIuH3fI/PPcuc HEJmCk/GkznG/UuQb1C7k3I/pUD5lZ2Mbp8tg064wiFGYviG1S+sW7dhqs/n3lnVxQIM ik8QP9GntoTrg0fS1uhapGfVjh787qnYWx6nbDqmhZ/De77eNbOpjghqdgiiG/9q8yGc q9wKEtwYSZCu9rsSc3bi6dxp7MiHZQ0Ot759glLKapwaDnvecK1apJ2dk4LVGhdu2JN0 wckw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5RCiLAeWSJzTzCoAPJIp4ghv9LaxaNUxgZhZVJHMMMw=; b=cYXi2ZfKKxmaX3SUo+0nbu21I+/hKRYspdgcSZBw7rtqBqR2cpBWfT68Q+bOyI86IC 5NRpSugQ1ZF0cvXRp8k0UqcWbl7byB3YJOHdqQCcG+Mve1hxQHl8+owoWxCN8OIdgrG9 L4OW9S6WHCtrvOxV0rcaVIXn2+YH3aCb0FlTlGDuOfqxE8cDWib6aY6xnPGEW2C1Hj6c 2X+SmLMJ24ViYq5FsYpPcvglLeLbr2AGTIY74HdNrz7sIY8OEAKRVJJ+I/2qMe8AZgHD CUi8uG0UDl1E5wdmxVLGM3Miv8w2kls6hQeub2ZHI0OdUT7JL4uhXd6O1XaV5X2EPkvF +fow== X-Gm-Message-State: ALoCoQm0W2gs2zfDxj9nFbt344cmCyzb4qe54yLNE+4OoOPzn6CSx6f3Olm6lyLo9GogNwlTqPd/ X-Received: by 10.98.14.67 with SMTP id w64mr75136473pfi.163.1448923420034; Mon, 30 Nov 2015 14:43:40 -0800 (PST) Received: from yshi-Precision-T5600.corp.ad.wrs.com (unknown-216-82.windriver.com. [147.11.216.82]) by smtp.gmail.com with ESMTPSA id 186sm25045398pfa.24.2015.11.30.14.43.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Nov 2015 14:43:39 -0800 (PST) From: Yang Shi To: ast@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, davem@davemloft.net Cc: zlim.lnx@gmail.com, xi.wang@gmail.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, yang.shi@linaro.org Subject: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction Date: Mon, 30 Nov 2015 14:24:07 -0800 Message-Id: <1448922247-5692-1-git-send-email-yang.shi@linaro.org> X-Mailer: git-send-email 2.0.2 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org aarch64 doesn't have native store immediate instruction, such operation has to be implemented by the below instruction sequence: Load immediate to register Store register Signed-off-by: Yang Shi CC: Zi Shen Lim CC: Xi Wang Reviewed-by: Zi Shen Lim --- Thsi patch might be buried by the storm of xadd discussion, however, it is absolutely irrelevent to xadd, so resend the patch itself. arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 6809647..49c1f1b 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -563,7 +563,25 @@ emit_cond_jmp: case BPF_ST | BPF_MEM | BPF_H: case BPF_ST | BPF_MEM | BPF_B: case BPF_ST | BPF_MEM | BPF_DW: - goto notyet; + /* Load imm to a register then store it */ + ctx->tmp_used = 1; + emit_a64_mov_i(1, tmp2, off, ctx); + emit_a64_mov_i(1, tmp, imm, ctx); + switch (BPF_SIZE(code)) { + case BPF_W: + emit(A64_STR32(tmp, dst, tmp2), ctx); + break; + case BPF_H: + emit(A64_STRH(tmp, dst, tmp2), ctx); + break; + case BPF_B: + emit(A64_STRB(tmp, dst, tmp2), ctx); + break; + case BPF_DW: + emit(A64_STR64(tmp, dst, tmp2), ctx); + break; + } + break; /* STX: *(size *)(dst + off) = src */ case BPF_STX | BPF_MEM | BPF_W: