From patchwork Thu Nov 26 18:08:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 549210 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8F0631402A5 for ; Fri, 27 Nov 2015 05:09:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=semihalf-com.20150623.gappssmtp.com header.i=@semihalf-com.20150623.gappssmtp.com header.b=CtzgLXZT; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753400AbbKZSJK (ORCPT ); Thu, 26 Nov 2015 13:09:10 -0500 Received: from mail-lf0-f45.google.com ([209.85.215.45]:33102 "EHLO mail-lf0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753312AbbKZSIa (ORCPT ); Thu, 26 Nov 2015 13:08:30 -0500 Received: by lfaz4 with SMTP id z4so105655750lfa.0 for ; Thu, 26 Nov 2015 10:08:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s3POvYBUifdgoS5oDorJ6WU5xzedyiE+BzXmZO/xbZg=; b=CtzgLXZTAROS5EETfumDz72mIZf3578fLl1K1+XgtSrGPtx0uNr/7/VRsp9UTvLR6/ D3qWzu2f4RyTpMDzMKTHypISvfAE6wOmWA+vcTBPx6c57AZytbrFunuiF+lLSDb5/B6i FqeHWHkOjge8MFfQfJNvuXY0kLNGCCxDALNFZG6K6R2WklWqi8k3omCJOL8c+TKrEAnX guoA76pDrG23g8sfCHPH9pLLhFdosErY9sY2nG53eJwykrzWMxOb2fBSQfL5eYipcSOZ scrk6vHpA15yqdoh5vrOmGVFNbu1rRPdQierd5LOjX0ZFHv+rKmwdHKTFbrP8+zrm2Cl PqIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s3POvYBUifdgoS5oDorJ6WU5xzedyiE+BzXmZO/xbZg=; b=h+UwU8TbWzkXmMoaggqujoi+Xuqvjl84Nsj5w2677eRgA197GvluyQZfhdtzLCkrzS 360p+dbw8hHuAV8YUSrqdKChYyjQLt/Qi4QdrkoLVXZe9V7ukf/gW3KjUy1sRFhCQCJ4 eqobUdysHX4MKIa7YAHBgzAv51EpfZAxzCwVBvN6yVvNTw5rSDbOC25zV1CeAICAS0SC g7fDSLpJ4fJDSCnzWWSZ7rTb0n7jJ7hFSm7lbmmB3s+J/RsK5hXacK8Zo9ozSU+WX4Zb zqcQfVSas/N06A0/VPVvc9pklJhLubKDsPisBi1cCyKFoUIt6+qMlQ47Uk0C3z28gsOw GdwQ== X-Gm-Message-State: ALoCoQlJGoLSTRlObz6Gqdx+Nt0F0Mxy/AnfGOROoQxRZbrL+2e01II6Af1aGLllQo7ccywk7BnM X-Received: by 10.25.21.80 with SMTP id l77mr3081157lfi.43.1448561308464; Thu, 26 Nov 2015 10:08:28 -0800 (PST) Received: from enkidu.semihalf.local ([80.82.22.190]) by smtp.gmail.com with ESMTPSA id a190sm4297654lfa.32.2015.11.26.10.08.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Nov 2015 10:08:27 -0800 (PST) From: Marcin Wojtas To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org Cc: davem@davemloft.net, linux@arm.linux.org.uk, sebastian.hesselbarth@gmail.com, andrew@lunn.ch, jason@lakedaemon.net, thomas.petazzoni@free-electrons.com, gregory.clement@free-electrons.com, simon.guinot@sequanux.org, nadavh@marvell.com, alior@marvell.com, xswang@marvell.com, myair@marvell.com, nitroshift@yahoo.com, mw@semihalf.com, jaz@semihalf.com, tn@semihalf.com, Subject: [PATCH v2 net 5/6] net: mvneta: enable setting custom TX IP checksum limit Date: Thu, 26 Nov 2015 19:08:12 +0100 Message-Id: <1448561293-16431-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1448561293-16431-1-git-send-email-mw@semihalf.com> References: <1448561293-16431-1-git-send-email-mw@semihalf.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since Armada 38x SoC can support IP checksum for jumbo frames only on a single port, it means that this feature should be enabled per-port, rather than for the whole SoC. This patch enables setting custom TX IP checksum limit by adding new optional property to the mvneta device tree node. If not used, by default 1600B is set for "marvell,armada-370-neta" and 9800B for other strings, which ensures backward compatibility. Binding documentation is updated accordingly. Signed-off-by: Marcin Wojtas Cc: # v3.18+ --- .../bindings/net/marvell-armada-370-neta.txt | 6 ++++++ drivers/net/ethernet/marvell/mvneta.c | 19 +++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt index f5a8ca2..aeea50c 100644 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt @@ -8,6 +8,11 @@ Required properties: - phy-mode: See ethernet.txt file in the same directory - clocks: a pointer to the reference clock for this device. +Optional properties: +- tx-csum-limit: maximum mtu supported by port that allow TX checksum. + Value is presented in bytes. If not used, by default 1600B is set for + "marvell,armada-370-neta" and 9800B for others. + Example: ethernet@d0070000 { @@ -15,6 +20,7 @@ ethernet@d0070000 { reg = <0xd0070000 0x2500>; interrupts = <8>; clocks = <&gate_clk 4>; + tx-csum-limit = <9800> status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 62cf971..32d6f28 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -243,6 +243,7 @@ #define MVNETA_VLAN_TAG_LEN 4 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 +#define MVNETA_TX_CSUM_DEF_SIZE 1600 #define MVNETA_TX_CSUM_MAX_SIZE 9800 #define MVNETA_ACC_MODE_EXT 1 @@ -3257,6 +3258,7 @@ static int mvneta_probe(struct platform_device *pdev) char hw_mac_addr[ETH_ALEN]; const char *mac_from; const char *managed; + int tx_csum_limit; int phy_mode; int err; int cpu; @@ -3357,8 +3359,21 @@ static int mvneta_probe(struct platform_device *pdev) } } - if (of_device_is_compatible(dn, "marvell,armada-370-neta")) - pp->tx_csum_limit = 1600; + if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { + if (tx_csum_limit < 0 || + tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { + tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; + dev_info(&pdev->dev, + "Wrong TX csum limit in DT, set to %dB\n", + MVNETA_TX_CSUM_DEF_SIZE); + } + } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { + tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; + } else { + tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; + } + + pp->tx_csum_limit = tx_csum_limit; pp->tx_ring_size = MVNETA_MAX_TXD; pp->rx_ring_size = MVNETA_MAX_RXD;