From patchwork Thu Nov 12 21:57:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Shi X-Patchwork-Id: 543719 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9FD4214142A for ; Fri, 13 Nov 2015 09:16:17 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro_org.20150623.gappssmtp.com header.i=@linaro_org.20150623.gappssmtp.com header.b=B+ItVZrs; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754283AbbKLWP4 (ORCPT ); Thu, 12 Nov 2015 17:15:56 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:34000 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754227AbbKLWPv (ORCPT ); Thu, 12 Nov 2015 17:15:51 -0500 Received: by padhx2 with SMTP id hx2so77705098pad.1 for ; Thu, 12 Nov 2015 14:15:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BzsLm5vPKjj9W+dp+n2jxOQuw2hzfzwd/YyvwzUHoAA=; b=B+ItVZrseumKdvr8p+vDJWR1TrOj/5f/DbgBLD7TclPDlVkw07CPL+8Au/Xr7FRbRF HB6lQCSbjohD0DV10lfUW50N75gjyS/CCrcvnjHdCgd/mN1J5tAh/43SKE+ZWAxOisF5 l3QuQWwwzZ6UAUCgfygFlqD8yjXzUqR0nF+mQKwtA8ZYY1wewvb7Q/vAkB6N7loT4Qnd A+94i0uPpstYPaFAaYcgTAOVY4NTsj8l5oSL39vJQ5IxOTufoSgNnqDyosbXqPA2XwSk HV5LtWmdNqOI9OH/uRpR/4e11nscWjv3G/nICDriXw2Jf+Bvg0WBrTnFwBuHxAqFrbqi 6sFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BzsLm5vPKjj9W+dp+n2jxOQuw2hzfzwd/YyvwzUHoAA=; b=SRWbO6cpuqTVxAJhxU931OKDgqS0eDSfvsih+a2B3JKvlVuYz/K3Z1P+W43Ak6l2aO 72n9E0dA3J9MsTuM71Yt5X4fqWR0zfKrTloFukPitcYis0KDu41gJezLZ+/t9sqejQWm 5EJ5r6tIATIj900oin+hLXwWWCZp43rw60380ifCa/jJrUNBiOUtRfY8qkr7RLqKAZ90 FbP1BMFaQtQuIHFdiPlRnBQ1U3BZDOrhmNNc1fD/4NRqGk4FscBr52YYbfrMTd7Pxhai 2dCOai1soRwxcQ+sxe7h1hpkPRBZXL8TWfufGCbgh5tMYARq6WZI6pkTocI3WjboOrqb mBvw== X-Gm-Message-State: ALoCoQkaTSsRphfYShhtHrmykU84HQEgGsbPz6OSKJFya7LMjZ/8bXpMaVkkG6YIzv/ge+VfZjC+ X-Received: by 10.66.228.137 with SMTP id si9mr26274736pac.63.1447366551093; Thu, 12 Nov 2015 14:15:51 -0800 (PST) Received: from yshi-Precision-T5600.corp.ad.wrs.com (unknown-216-82.windriver.com. [147.11.216.82]) by smtp.gmail.com with ESMTPSA id ur1sm829267pbc.44.2015.11.12.14.15.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Nov 2015 14:15:50 -0800 (PST) From: Yang Shi To: ast@kernel.org, daniel@iogearbox.net, catalin.marinas@arm.com, will.deacon@arm.com Cc: zlim.lnx@gmail.com, xi.wang@gmail.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, yang.shi@linaro.org Subject: [PATCH 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS Date: Thu, 12 Nov 2015 13:57:01 -0800 Message-Id: <1447365421-1309-3-git-send-email-yang.shi@linaro.org> X-Mailer: git-send-email 2.0.2 In-Reply-To: <1447365421-1309-1-git-send-email-yang.shi@linaro.org> References: <1447365421-1309-1-git-send-email-yang.shi@linaro.org> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to change during function call so it may cause the BPF prog stack base address change too. Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee saved register, so it will keep intact during function call. It is initialized in BPF prog prologue when BPF prog is started to run everytime. When BPF prog exits, it could be just tossed. So, the BPF stack layout looks like: high original A64_SP => 0:+-----+ BPF prologue | | FP/LR and callee saved registers BPF fp register => -64:+-----+ | | | ... | BPF prog stack | | | | current A64_SP/FP => +-----+ | | | ... | Function call stack | | +-----+ low CC: Zi Shen Lim CC: Xi Wang Signed-off-by: Yang Shi --- arch/arm64/net/bpf_jit_comp.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index ac8b548..8753bb7 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -50,7 +50,7 @@ static const int bpf2a64[] = { [BPF_REG_8] = A64_R(21), [BPF_REG_9] = A64_R(22), /* read-only frame pointer to access stack */ - [BPF_REG_FP] = A64_FP, + [BPF_REG_FP] = A64_R(25), /* temporary register for internal BPF JIT */ [TMP_REG_1] = A64_R(23), [TMP_REG_2] = A64_R(24), @@ -155,17 +155,41 @@ static void build_prologue(struct jit_ctx *ctx) stack_size += 4; /* extra for skb_copy_bits buffer */ stack_size = STACK_ALIGN(stack_size); + /* + * BPF prog stack layout + * + * high + * original A64_SP => 0:+-----+ BPF prologue + * | | FP/LR and callee saved registers + * BPF fp register => -64:+-----+ + * | | + * | ... | BPF prog stack + * | | + * | | + * current A64_SP/FP => +-----+ + * | | + * | ... | Function call stack + * | | + * +-----+ + * low + * + */ + + /* Save FP and LR registers to stay align with ARM64 AAPCS */ + emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); + /* Save callee-saved register */ emit(A64_PUSH(r6, r7, A64_SP), ctx); emit(A64_PUSH(r8, r9, A64_SP), ctx); if (ctx->tmp_used) emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx); - /* Set up frame pointer */ + /* Set up BPF prog stack base register (x25) */ emit(A64_MOV(1, fp, A64_SP), ctx); - /* Set up BPF stack */ + /* Set up function call stack */ emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); + emit(A64_MOV(1, A64_FP, A64_SP), ctx); /* Clear registers A and X */ emit_a64_mov_i64(ra, 0, ctx); @@ -196,8 +220,8 @@ static void build_epilogue(struct jit_ctx *ctx) emit(A64_POP(r8, r9, A64_SP), ctx); emit(A64_POP(r6, r7, A64_SP), ctx); - /* Restore frame pointer */ - emit(A64_MOV(1, fp, A64_SP), ctx); + /* Restore FP/LR registers */ + emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); /* Set return value */ emit(A64_MOV(1, A64_R(0), r0), ctx);