From patchwork Tue Nov 10 22:41:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Shi X-Patchwork-Id: 542647 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 484C31413F8 for ; Wed, 11 Nov 2015 10:01:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro_org.20150623.gappssmtp.com header.i=@linaro_org.20150623.gappssmtp.com header.b=AzmCgcYK; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752151AbbKJXA4 (ORCPT ); Tue, 10 Nov 2015 18:00:56 -0500 Received: from mail-pa0-f51.google.com ([209.85.220.51]:35267 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751623AbbKJXAW (ORCPT ); Tue, 10 Nov 2015 18:00:22 -0500 Received: by pasz6 with SMTP id z6so10945914pas.2 for ; Tue, 10 Nov 2015 15:00:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LxxOLTEFSExeYixZYFW9vwwvihNdl5MGLdtg1RymEgw=; b=AzmCgcYKzvvazxXTko1S+StQsZEexlrPpxMN/lQBNlW76GB7pmQ4TEzUv8dOOsX99S ssqqi6QvzexZ4xK9yhO22vZ7vSQ79NFxpugxkSPQ7619sBbj0xCO/v4VvHpL+j9f/qxk +z+p5esTuY62vZ+5fJiN6p0+T9k4ZHqERXGMRKVhKvXw6DBDZms44U9ZF/3lKnVV9B6m P4r7k+oAETQ6bqc818dxyWpD3pH9yRwPfsobGNqvlbB7pcVhC25i4J880Hfm1E1N+Uhk RogpWeB4Uo4mfKpn0hdEYS6jj4+uYJlYsF21EJBc9LqETebWJ8I1GEUOa8QlhQbM+j6r vimQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LxxOLTEFSExeYixZYFW9vwwvihNdl5MGLdtg1RymEgw=; b=InsF00qPVV7hf/iWLwX0G6HuAc7NZ561ZaI84T5xgqRcnsYWNvAJVtKT6jQA1VcpMJ 2TAqA50PAZwIHz0/Q69Cln1YeUekHi63Lh9KixSdYZlEPOEXBGPuq9mbW6ihUJPIJOK6 sU0f4P1c4k1ZfJ36yxQkTZ677hPdS0z672LN0yOhz/4Dv3rQeN+IJoaThwist3tLAs5C msouyxNX20/VGXonZ3OwRO1UzflVvL2vW/rnTBSOzgEBlUmWrYejwHSo6M6PG91fZgGx gCEbGoKUrehazDbYk13i0O7bB1dl9ZXPheA0YJ2MANjh4fxGESqT4APkAkwJJPd1c4KB T+kQ== X-Gm-Message-State: ALoCoQlcOK4Dscys+Rh5dBqc5d2LLq8KND2c39C7RbvvVUjTXoNfZAh8Fkx8uFHPu7KtBF/X1kC2 X-Received: by 10.68.203.132 with SMTP id kq4mr9604241pbc.82.1447196422268; Tue, 10 Nov 2015 15:00:22 -0800 (PST) Received: from yshi-Precision-T5600.corp.ad.wrs.com (unknown-216-82.windriver.com. [147.11.216.82]) by smtp.gmail.com with ESMTPSA id c5sm6102743pbu.18.2015.11.10.15.00.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Nov 2015 15:00:21 -0800 (PST) From: Yang Shi To: ast@kernel.org, daniel@iogearbox.net, catalin.marinas@arm.com, will.deacon@arm.com Cc: zlim.lnx@gmail.com, xi.wang@gmail.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, yang.shi@linaro.org Subject: [PATCH 1/2] arm64: bpf: add 'store immediate' instruction Date: Tue, 10 Nov 2015 14:41:40 -0800 Message-Id: <1447195301-16757-2-git-send-email-yang.shi@linaro.org> X-Mailer: git-send-email 2.0.2 In-Reply-To: <1447195301-16757-1-git-send-email-yang.shi@linaro.org> References: <1447195301-16757-1-git-send-email-yang.shi@linaro.org> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org aarch64 doesn't have native store immediate instruction, such operation has to be implemented by the below instruction sequence: Load immediate to register Store register Signed-off-by: Yang Shi CC: Zi Shen Lim CC: Xi Wang Reviewed-by: Zi Shen Lim --- arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 6809647..49c1f1b 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -563,7 +563,25 @@ emit_cond_jmp: case BPF_ST | BPF_MEM | BPF_H: case BPF_ST | BPF_MEM | BPF_B: case BPF_ST | BPF_MEM | BPF_DW: - goto notyet; + /* Load imm to a register then store it */ + ctx->tmp_used = 1; + emit_a64_mov_i(1, tmp2, off, ctx); + emit_a64_mov_i(1, tmp, imm, ctx); + switch (BPF_SIZE(code)) { + case BPF_W: + emit(A64_STR32(tmp, dst, tmp2), ctx); + break; + case BPF_H: + emit(A64_STRH(tmp, dst, tmp2), ctx); + break; + case BPF_B: + emit(A64_STRB(tmp, dst, tmp2), ctx); + break; + case BPF_DW: + emit(A64_STR64(tmp, dst, tmp2), ctx); + break; + } + break; /* STX: *(size *)(dst + off) = src */ case BPF_STX | BPF_MEM | BPF_W: