From patchwork Sun Jun 21 19:52:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 487077 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4749B140311 for ; Mon, 22 Jun 2015 05:54:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754886AbbFUTx1 (ORCPT ); Sun, 21 Jun 2015 15:53:27 -0400 Received: from gloria.sntech.de ([95.129.55.99]:55207 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751805AbbFUTxG (ORCPT ); Sun, 21 Jun 2015 15:53:06 -0400 Received: from [95.91.187.196] (helo=diego.lan) by gloria.sntech.de with esmtpsa (TLS1.1:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1Z6lIZ-0007eC-0u; Sun, 21 Jun 2015 21:52:59 +0200 From: Heiko Stuebner To: peppe.cavallaro@st.com, davem@davemloft.net Cc: roger.chen@rock-chips.com, linux-rockchip@lists.infradead.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Heiko Stuebner , stable@vger.kernel.org Subject: [PATCH v2 2/4] net: stmmac: dwmac-rk: Fix clk rate when provided by soc Date: Sun, 21 Jun 2015 21:52:52 +0200 Message-Id: <1434916374-7457-3-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1434916374-7457-1-git-send-email-heiko@sntech.de> References: <1434916374-7457-1-git-send-email-heiko@sntech.de> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The first iteration of the dwmac-rk support did access an intermediate clock directly below the pll selector. This was removed in a subsequent revision, but the clock and one invocation remained. This results in the driver trying to set the rate of a non-existent clock when the soc and not some external source provides the phy clock for RMII phys. So set the rate of the correct clock and remove the remaining now completely unused definition. Fixes: 436f5ae08f9d ("GMAC: add driver for Rockchip RK3288 SoCs integrated GMAC") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner --- drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index a396070..5dafebb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -42,7 +42,6 @@ struct rk_priv_data { bool clock_input; struct clk *clk_mac; - struct clk *clk_mac_pll; struct clk *gmac_clkin; struct clk *mac_clk_rx; struct clk *mac_clk_tx; @@ -209,7 +208,7 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv) dev_info(dev, "clock input from PHY\n"); } else { if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) - clk_set_rate(bsp_priv->clk_mac_pll, 50000000); + clk_set_rate(bsp_priv->clk_mac, 50000000); } return 0;