From patchwork Thu Feb 26 11:01:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Chandran X-Patchwork-Id: 443884 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D3A2E14007D for ; Thu, 26 Feb 2015 22:02:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753190AbbBZLBe (ORCPT ); Thu, 26 Feb 2015 06:01:34 -0500 Received: from mail-pa0-f53.google.com ([209.85.220.53]:37200 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751344AbbBZLBd (ORCPT ); Thu, 26 Feb 2015 06:01:33 -0500 Received: by pabrd3 with SMTP id rd3so13168910pab.4 for ; Thu, 26 Feb 2015 03:01:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=witHkMVFSzmY3Btrmh7+DvQ3MXhaXCwglagyPAqUuvU=; b=BvyPvYw8f+JHjfp8ZD6L4hETPbRybI3GddsK0siV046jUk3NruzqjFi/vry+/M7xHo AK3fXoqhfGmtcMo87vTf7n0tN+ktKmFc71eBOmtA7s76m/Umt32UXAl6zp9y0Q+ddYZh 6TufhpA5QN4nYWKWWg42Z+3c6QEsOjSqFTDtSBGUNiIEnYkuRz/7KnaiozyqsduVjBG0 79Us3eyhhsK9j81r3cSowUALHwZmQYqRkXVTzNDpKngvsv7tjzkWLeDc2mC5hYUgy7ks 1FRGsnl3ZEclbaD4aM5x81Yz9uhp1hpeUmypH7rPiQjgBGxiELxFiE2bADi757L1bRTJ RWvA== X-Gm-Message-State: ALoCoQkgOpLXU5ixvLwTJS8MoAIiz4EldRpYX2TnhW4ZVVWtYUtaDo3Uf/kSNPN5IbL/0BvTXbo2 X-Received: by 10.68.164.3 with SMTP id ym3mr13746048pbb.100.1424948493243; Thu, 26 Feb 2015 03:01:33 -0800 (PST) Received: from arun-OptiPlex-9010.mvista.com ([111.93.218.67]) by mx.google.com with ESMTPSA id qa1sm596837pdb.84.2015.02.26.03.01.30 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Feb 2015 03:01:32 -0800 (PST) From: Arun Chandran To: Nicolas Ferre , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michal Simek Cc: Arun Chandran Subject: [PATCH v3] net: macb: Add big endian CPU support Date: Thu, 26 Feb 2015 16:31:14 +0530 Message-Id: <1424948474-11872-1-git-send-email-achandran@mvista.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <54EEF9C6.8070701@monstr.eu> References: <54EEF9C6.8070701@monstr.eu> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch converts all __raw_readl and __raw_writel function calls to their corresponding readl_relaxed and writel_relaxed variants. It also tells the driver to set ahb_endian_swp_mgmt_en bit in dma_cfg when the CPU is configured in big endian mode. Signed-off-by: Arun Chandran Acked-by: Nicolas Ferre Tested-by: Michal Simek --- This patch is tested on xilinx ZC702 evaluation board with CONFIG_CPU_BIG_ENDIAN=y and booting NFS rootfs changes since initial version: * Added on the fly CPU endianness detection according to comments from Michal Simek. * Corrected GEM_* defines as per comments from Nicolas Ferre. --- --- drivers/net/ethernet/cadence/macb.c | 32 ++++++++++++++++++++++++++------ drivers/net/ethernet/cadence/macb.h | 18 ++++++++++-------- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index ad76b8e..1fe8b94 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -449,7 +449,7 @@ static void macb_update_stats(struct macb *bp) WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); for(; p < end; p++, reg++) - *p += __raw_readl(reg); + *p += readl_relaxed(reg); } static int macb_halt_tx(struct macb *bp) @@ -1578,6 +1578,7 @@ static u32 macb_dbw(struct macb *bp) static void macb_configure_dma(struct macb *bp) { u32 dmacfg; + u32 tmp, ncr; if (macb_is_gem(bp)) { dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); @@ -1585,7 +1586,24 @@ static void macb_configure_dma(struct macb *bp) if (bp->dma_burst_length) dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); - dmacfg &= ~GEM_BIT(ENDIA); + dmacfg &= ~GEM_BIT(ENDIA_PKT); + + /* Find the CPU endianness by using the loopback bit of net_ctrl + * register. save it first. When the CPU is in big endian we + * need to program swaped mode for management descriptor access. + */ + ncr = macb_readl(bp, NCR); + __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR); + tmp = __raw_readl(bp->regs + MACB_NCR); + + if (tmp == MACB_BIT(LLB)) + dmacfg &= ~GEM_BIT(ENDIA_DESC); + else + dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ + + /* Restore net_ctrl */ + macb_writel(bp, NCR, ncr); + if (bp->dev->features & NETIF_F_HW_CSUM) dmacfg |= GEM_BIT(TXCOEN); else @@ -1832,14 +1850,14 @@ static void gem_update_stats(struct macb *bp) for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { u32 offset = gem_statistics[i].offset; - u64 val = __raw_readl(bp->regs + offset); + u64 val = readl_relaxed(bp->regs + offset); bp->ethtool_stats[i] += val; *p += val; if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { /* Add GEM_OCTTXH, GEM_OCTRXH */ - val = __raw_readl(bp->regs + offset + 4); + val = readl_relaxed(bp->regs + offset + 4); bp->ethtool_stats[i] += ((u64)val) << 32; *(++p) += val; } @@ -2191,12 +2209,14 @@ static void macb_probe_queues(void __iomem *mem, *num_queues = 1; /* is it macb or gem ? */ - mid = __raw_readl(mem + MACB_MID); + mid = readl_relaxed(mem + MACB_MID); + if (MACB_BFEXT(IDNUM, mid) != 0x2) return; /* bit 0 is never set but queue 0 always exists */ - *queue_mask = __raw_readl(mem + GEM_DCFG6) & 0xff; + *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff; + *queue_mask |= 0x1; for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 31dc080..83241c8 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -229,8 +229,10 @@ /* Bitfields in DMACFG. */ #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ #define GEM_FBLDO_SIZE 5 -#define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */ -#define GEM_ENDIA_SIZE 1 +#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ +#define GEM_ENDIA_DESC_SIZE 1 +#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ +#define GEM_ENDIA_PKT_SIZE 1 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ #define GEM_RXBMS_SIZE 2 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ @@ -423,17 +425,17 @@ /* Register access macros */ #define macb_readl(port,reg) \ - __raw_readl((port)->regs + MACB_##reg) + readl_relaxed((port)->regs + MACB_##reg) #define macb_writel(port,reg,value) \ - __raw_writel((value), (port)->regs + MACB_##reg) + writel_relaxed((value), (port)->regs + MACB_##reg) #define gem_readl(port, reg) \ - __raw_readl((port)->regs + GEM_##reg) + readl_relaxed((port)->regs + GEM_##reg) #define gem_writel(port, reg, value) \ - __raw_writel((value), (port)->regs + GEM_##reg) + writel_relaxed((value), (port)->regs + GEM_##reg) #define queue_readl(queue, reg) \ - __raw_readl((queue)->bp->regs + (queue)->reg) + readl_relaxed((queue)->bp->regs + (queue)->reg) #define queue_writel(queue, reg, value) \ - __raw_writel((value), (queue)->bp->regs + (queue)->reg) + writel_relaxed((value), (queue)->bp->regs + (queue)->reg) /* Conditional GEM/MACB macros. These perform the operation to the correct * register dependent on whether the device is a GEM or a MACB. For registers