From patchwork Wed Feb 18 11:29:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Chandran X-Patchwork-Id: 440922 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 54C28140082 for ; Wed, 18 Feb 2015 22:30:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751402AbbBRLaA (ORCPT ); Wed, 18 Feb 2015 06:30:00 -0500 Received: from mail-pa0-f45.google.com ([209.85.220.45]:32906 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750976AbbBRL36 (ORCPT ); Wed, 18 Feb 2015 06:29:58 -0500 Received: by pabkx10 with SMTP id kx10so633602pab.0 for ; Wed, 18 Feb 2015 03:29:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6FJNkz1cIcb6u7sCSS2qLgSoOEVRMxqwLEorCfIv/4w=; b=LHOlnmhDhVXboKetJc90v6jAmf7e5K9d8uiMWZf3Xb1wb9s40mi3ZsHj5rtr/+wi3e n7hOwOoP0F3Ima0+sD/61T9VVTApJVrZpfz3qOGAjv8Aa8QKEUdNv6FJIr0rpQYUGvuR lI9S7wZ0Y2JaWuhobvE5sCtf52SEb2H5Poz5eik5vYF1mYuhhjampKgKxtzRJWgEeCOf Xs0SPGt4Noic7xEP0PwNRU8HX1PtNfo7Ji8PZv/d7FIihIq+TyiPZcQvqMR9Mpt2zasA I+b/288901YRkeWidqeMItCOuJiDkPlEBIU5K0W+rGr3bX79f5kPH9B6XdlKALmcvckR s+1A== X-Gm-Message-State: ALoCoQlpLwvJ+fudSqzdhU3Oat4DYQ1DUOyB1T0ZGg5Cgkhfy4wwBd+XSjyS1GhVZIgxmfeYMpEM X-Received: by 10.66.250.196 with SMTP id ze4mr11391693pac.32.1424258998108; Wed, 18 Feb 2015 03:29:58 -0800 (PST) Received: from arun-OptiPlex-9010.mvista.com ([111.93.218.67]) by mx.google.com with ESMTPSA id di5sm20371606pbc.36.2015.02.18.03.29.56 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Feb 2015 03:29:57 -0800 (PST) From: Arun Chandran To: Nicolas Ferre , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Arun Chandran Subject: [PATCH] net: macb: Add big endian CPU support Date: Wed, 18 Feb 2015 16:59:35 +0530 Message-Id: <1424258975-28611-1-git-send-email-achandran@mvista.com> X-Mailer: git-send-email 1.9.1 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch converts all __raw_readl and __raw_writel function calls to their corresponding readl_relaxed and writel_relaxed variants. It also tells the driver to set ahb_endian_swp_mgmt_en bit in dma_cfg when the CPU is configured in big endian mode. Signed-off-by: Arun Chandran Acked-by: Nicolas Ferre --- This patch is tested on xilinx ZC702 evaluation board with CONFIG_CPU_BIG_ENDIAN=y and booting NFS rootfs --- --- drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++------ drivers/net/ethernet/cadence/macb.h | 15 ++++++++------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index ad76b8e..05fb36d 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -449,7 +449,7 @@ static void macb_update_stats(struct macb *bp) WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); for(; p < end; p++, reg++) - *p += __raw_readl(reg); + *p += readl_relaxed(reg); } static int macb_halt_tx(struct macb *bp) @@ -1585,7 +1585,11 @@ static void macb_configure_dma(struct macb *bp) if (bp->dma_burst_length) dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); - dmacfg &= ~GEM_BIT(ENDIA); + dmacfg &= ~GEM_BIT(ENDIA_PKT); + /* Tell the chip to byteswap descriptors on big-endian hosts */ +#ifdef __BIG_ENDIAN + dmacfg |= GEM_BIT(ENDIA_DESC); +#endif if (bp->dev->features & NETIF_F_HW_CSUM) dmacfg |= GEM_BIT(TXCOEN); else @@ -1832,14 +1836,14 @@ static void gem_update_stats(struct macb *bp) for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { u32 offset = gem_statistics[i].offset; - u64 val = __raw_readl(bp->regs + offset); + u64 val = readl_relaxed(bp->regs + offset); bp->ethtool_stats[i] += val; *p += val; if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { /* Add GEM_OCTTXH, GEM_OCTRXH */ - val = __raw_readl(bp->regs + offset + 4); + val = readl_relaxed(bp->regs + offset + 4); bp->ethtool_stats[i] += ((u64)val) << 32; *(++p) += val; } @@ -2191,12 +2195,14 @@ static void macb_probe_queues(void __iomem *mem, *num_queues = 1; /* is it macb or gem ? */ - mid = __raw_readl(mem + MACB_MID); + mid = readl_relaxed(mem + MACB_MID); + if (MACB_BFEXT(IDNUM, mid) != 0x2) return; /* bit 0 is never set but queue 0 always exists */ - *queue_mask = __raw_readl(mem + GEM_DCFG6) & 0xff; + *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff; + *queue_mask |= 0x1; for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 31dc080..57f0a1a 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -229,7 +229,8 @@ /* Bitfields in DMACFG. */ #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ #define GEM_FBLDO_SIZE 5 -#define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */ +#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ +#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ #define GEM_ENDIA_SIZE 1 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ #define GEM_RXBMS_SIZE 2 @@ -423,17 +424,17 @@ /* Register access macros */ #define macb_readl(port,reg) \ - __raw_readl((port)->regs + MACB_##reg) + readl_relaxed((port)->regs + MACB_##reg) #define macb_writel(port,reg,value) \ - __raw_writel((value), (port)->regs + MACB_##reg) + writel_relaxed((value), (port)->regs + MACB_##reg) #define gem_readl(port, reg) \ - __raw_readl((port)->regs + GEM_##reg) + readl_relaxed((port)->regs + GEM_##reg) #define gem_writel(port, reg, value) \ - __raw_writel((value), (port)->regs + GEM_##reg) + writel_relaxed((value), (port)->regs + GEM_##reg) #define queue_readl(queue, reg) \ - __raw_readl((queue)->bp->regs + (queue)->reg) + readl_relaxed((queue)->bp->regs + (queue)->reg) #define queue_writel(queue, reg, value) \ - __raw_writel((value), (queue)->bp->regs + (queue)->reg) + writel_relaxed((value), (queue)->bp->regs + (queue)->reg) /* Conditional GEM/MACB macros. These perform the operation to the correct * register dependent on whether the device is a GEM or a MACB. For registers