From patchwork Tue Dec 16 10:28:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhu Yanjun X-Patchwork-Id: 421846 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BF916140119 for ; Tue, 16 Dec 2014 21:28:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751483AbaLPK2u (ORCPT ); Tue, 16 Dec 2014 05:28:50 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:47841 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751116AbaLPK2s (ORCPT ); Tue, 16 Dec 2014 05:28:48 -0500 Received: by mail-pa0-f49.google.com with SMTP id eu11so13764504pac.22 for ; Tue, 16 Dec 2014 02:28:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cjOGKWGu4Y1C8iP5KVZAqtA4UftTvTl5QRtlFvUxfs4=; b=urDCRokzB6qMtymMjJm9tyF8NddKRWgiskkSbi8INlOElqlu/Gq09Rj6GyMP5kNTdO f1IhyXRMyw2du9/gfRDBJPrhorsVGhVQ+MHKpKn2By+HzssyEqVlg+gmjz+N30GUNPnF zy+lBh4NYIAgHNlonn7hmYJmVbZc0lwjJhW031u9sD9AMCAICSAu6EGZLcPDdVlTtR4y 5duOkzyJAIsQ9ytOKHCU7xs30aL19E7nunrVnvAjh6ZurTR7oSNhw6SyCOPPeak1ilsz fsrFVRzbtN+iw/omLnVR5Sy7B1xeg4JY7fy+iJd+0eoWPwA0TU5zMOv5u2psUUDZHV2v 9ZAQ== X-Received: by 10.68.129.197 with SMTP id ny5mr59279074pbb.34.1418725728122; Tue, 16 Dec 2014 02:28:48 -0800 (PST) Received: from wind-OptiPlex-780.corp.ad.wrs.com ([106.120.101.38]) by mx.google.com with ESMTPSA id oq6sm538666pdb.45.2014.12.16.02.28.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 Dec 2014 02:28:47 -0800 (PST) From: Zhu Yanjun X-Google-Original-From: Zhu Yanjun To: netdev@vger.kernel.org, w@1wt.eu, zyjzyj2000@gmail.com Cc: Zhu Yanjun , Bruce Allan , Jeff Kirsher Subject: [PATCH 3/5] e1000e: do not toggle LANPHYPC value bit when PHY reset is blocked Date: Tue, 16 Dec 2014 18:28:18 +0800 Message-Id: <1418725700-31465-4-git-send-email-Yanjun.Zhu@windriver.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1418725700-31465-1-git-send-email-Yanjun.Zhu@windriver.com> References: <1418725700-31465-1-git-send-email-Yanjun.Zhu@windriver.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org 2.6.x kernels require a similar logic change as commit 6cc7aae [e1000e: do not toggle LANPHYPC value bit when PHY reset is blocked] introduces for newer kernels. When PHY reset is intentionally blocked on 82577/8/9, do not toggle the LANPHYPC value bit (essentially performing a hard power reset of the device) otherwise the PHY can be put into an unknown state. Cleanup whitespace in the same function. [yanjun.zhu: whitespace remains unchanged] Signed-off-by: Bruce Allan Tested-by: Jeff Pieper Signed-off-by: Jeff Kirsher Signed-off-by: Zhu Yanjun --- drivers/net/e1000e/ich8lan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index c4b2d15..8c7e4aa 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -280,7 +280,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked; phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; - if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { + if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID) && + !e1000_check_reset_block(hw)) { /*Set Phy Config Counter to 50msec */ ctrl = er32(FEXTNVM3); ctrl &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;