From patchwork Mon Dec 15 08:39:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhu Yanjun X-Patchwork-Id: 421004 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 984CD1400D2 for ; Mon, 15 Dec 2014 19:39:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751730AbaLOIjn (ORCPT ); Mon, 15 Dec 2014 03:39:43 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:49533 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751639AbaLOIjm (ORCPT ); Mon, 15 Dec 2014 03:39:42 -0500 Received: by mail-pa0-f44.google.com with SMTP id et14so11495453pad.3 for ; Mon, 15 Dec 2014 00:39:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7X+5AjM/0orWWlU5vNOdZkslVJjCT6F7HcGnQlbeNqA=; b=m47LWgTvNJfEYWKOdlKnkLQv94OBoJFvygrfqXLsSefxY4Nb/5mIaK1hq4ZGdAp+oK MKmGx6W5CBIrdtxB/ho4Oxzp9c0melWsZtl8j2OhA3R6gHEMWLsubG6WrsDUFVY+REdv 0eCQg0PWR0i8TBZgCiz6AlPo1f0sMsyrEKlcpfpY7crm2MYbzJRf78x947zPp8mBR1Fi JSH0GTLGnhNhrzIe2Pn0nJRnzoclfrDnOo8ILsF2Tw63hq+TTSiXHDtk4o+G5k0T95+J 8MJntIe75WRTBISa3bIJ2scIwf+5TmaxO1yA02DtcMbR6eIJrt4YwvSpmqYfeUULwPnY SBOw== X-Received: by 10.66.227.41 with SMTP id rx9mr48949230pac.153.1418632782399; Mon, 15 Dec 2014 00:39:42 -0800 (PST) Received: from wind-OptiPlex-780.corp.ad.wrs.com ([106.120.101.38]) by mx.google.com with ESMTPSA id wf5sm8560115pab.40.2014.12.15.00.39.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Dec 2014 00:39:41 -0800 (PST) From: Zhu Yanjun X-Google-Original-From: Zhu Yanjun To: netdev@vger.kernel.org, w@1wt.eu, zyjzyj2000@gmail.com Cc: Zhu Yanjun , Bruce Allan , Jeff Kirsher Subject: [PATCH 2/5] e1000e: workaround EEPROM configuration change on 82579 on kernel 2.6.x Date: Mon, 15 Dec 2014 16:39:11 +0800 Message-Id: <1418632754-16698-3-git-send-email-Yanjun.Zhu@windriver.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1418632754-16698-1-git-send-email-Yanjun.Zhu@windriver.com> References: <1418632754-16698-1-git-send-email-Yanjun.Zhu@windriver.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org 2.6.x kernels require a similar logic change as commit 62f1d8d1 [e1000e: workaround EEPROM configuration change on 82579] introduces for newer kernels. An update to the EEPROM on 82579 will extend a delay in hardware to fix an issue with WoL not working after a G3->S5 transition which is unrelated to the driver. However, this extended delay conflicts with nominal operation of the device when it is initialized by the driver and after every reset of the hardware (i.e. the driver starts configuring the device before the hardware is done with it's own configuration work). The workaround for when the driver is in control of the device is to tell the hardware after every reset the configuration delay should be the original shorter one. Some pre-existing variables are renamed generically to be re-used with new register accesses. [e1000_toggle_lanphypc_value_ich8lan does not exist. Its implementations exist in e1000_init_phy_params_pchlan. Renamed variables remain unchanged] Signed-off-by: Bruce Allan Tested-by: Jeff Pieper Signed-off-by: Jeff Kirsher Signed-off-by: Zhu Yanjun --- drivers/net/e1000e/hw.h | 1 + drivers/net/e1000e/ich8lan.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index 11f3b7c..b055d78 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h @@ -60,6 +60,7 @@ enum e1e_registers { E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */ E1000_FCT = 0x00030, /* Flow Control Type - RW */ E1000_VET = 0x00038, /* VLAN Ether Type - RW */ + E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */ E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */ E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */ E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */ diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 020657c..c4b2d15 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -108,6 +108,9 @@ #define E1000_FEXTNVM_SW_CONFIG 1 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ +#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 +#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 + #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL #define E1000_ICH_RAR_ENTRIES 7 @@ -278,6 +281,12 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { + /*Set Phy Config Counter to 50msec */ + ctrl = er32(FEXTNVM3); + ctrl &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; + ctrl |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; + ew32(FEXTNVM3, ctrl); + /* * The MAC-PHY interconnect may still be in SMBus mode * after Sx->S0. Toggle the LANPHYPC Value bit to force @@ -2685,6 +2694,14 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ew32(CTRL, (ctrl | E1000_CTRL_RST)); msleep(20); + /* Set Phy Config Counter to 50msec */ + if (hw->mac.type == e1000_pch2lan) { + u32 phycc_reg = er32(FEXTNVM3); + phycc_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; + phycc_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; + ew32(FEXTNVM3, phycc_reg); + } + if (!ret_val) e1000_release_swflag_ich8lan(hw);