From patchwork Mon Dec 15 08:39:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhu Yanjun X-Patchwork-Id: 421003 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2C6B91400DD for ; Mon, 15 Dec 2014 19:39:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751704AbaLOIjj (ORCPT ); Mon, 15 Dec 2014 03:39:39 -0500 Received: from mail-pd0-f171.google.com ([209.85.192.171]:56177 "EHLO mail-pd0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751662AbaLOIji (ORCPT ); Mon, 15 Dec 2014 03:39:38 -0500 Received: by mail-pd0-f171.google.com with SMTP id y13so11245944pdi.16 for ; Mon, 15 Dec 2014 00:39:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fDluz3u2nJ8VO27MkygEtobHyyrGS6XuqVsOCT264U0=; b=qSKL1w2aPY7B5gNSGpZ9MwsnQNzKCM+LHr4F1xZCMyNfv8s0uNwKCfEAZhfrTnWDoW c+tUE6ZGsqwmpieegk44aBAfKI/f6vsVnIlAv8ZfMA6zAuxtgyb+aYSAJ53KvdVo8w4j q2SBayXM58QIbJx9O6J+c8lHga4ixrZo5LLDNaBqVBzzcepN0PDgQnkXZbTOUx3FbeKW +cWYTZzR7bTclB45c0DX58F0B2azyx/r24hRSuRGja4Ri+Fpn3NtaOldvLMn8EUyYTnQ vsQ3P2nuaKck66IGkG70iFqz9gmunulYpbm5/6M8bgxUCjBG8c4DGenn2hp2YV6iUSHp tXfw== X-Received: by 10.66.120.129 with SMTP id lc1mr49677572pab.86.1418632777693; Mon, 15 Dec 2014 00:39:37 -0800 (PST) Received: from wind-OptiPlex-780.corp.ad.wrs.com ([106.120.101.38]) by mx.google.com with ESMTPSA id wf5sm8560115pab.40.2014.12.15.00.39.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Dec 2014 00:39:36 -0800 (PST) From: Zhu Yanjun X-Google-Original-From: Zhu Yanjun To: netdev@vger.kernel.org, w@1wt.eu, zyjzyj2000@gmail.com Cc: Zhu Yanjun , Bruce Allan , Jeff Kirsher , "David S. Miller" Subject: [PATCH 1/5] e1000e: reset MAC-PHY interconnect on 82577/82578 Date: Mon, 15 Dec 2014 16:39:10 +0800 Message-Id: <1418632754-16698-2-git-send-email-Yanjun.Zhu@windriver.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1418632754-16698-1-git-send-email-Yanjun.Zhu@windriver.com> References: <1418632754-16698-1-git-send-email-Yanjun.Zhu@windriver.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org 2.6.x kernels require a similar logic change as commit 901b2b95 [e1000e: reset MAC-PHY interconnect on 82577/82578] introduces for newer kernels. During Sx->S0 transitions, the interconnect between the MAC and PHY on 82577/82578 can remain in SMBus mode instead of transitioning to the PCIe-like mode required during normal operation. Toggling the LANPHYPC Value bit essentially resets the interconnect forcing it to the correct mode. after review of all intel drivers, found several instances where drivers had the incorrect pattern of: memory mapped write(); delay(); which should always be: memory mapped write(); write flush(); /* aka memory mapped read */ delay(); explanation: The reason for including the flush is that writes can be held (posted) in PCI/PCIe bridges, but the read always has to complete synchronously and therefore has to flush all pending writes to a device. If a write is held and followed by a delay, the delay means nothing because the write may not have reached hardware (maybe even not until the next read) Signed-off-by: Bruce Allan Signed-off-by: Jeff Kirsher Signed-off-by: David S. Miller Signed-off-by: Zhu Yanjun --- drivers/net/e1000e/defines.h | 2 ++ drivers/net/e1000e/ich8lan.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 1190167..52283a6 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -214,6 +214,8 @@ #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ +#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index de39f9a..020657c 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -88,6 +88,8 @@ #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ +/* FW established a valid mode */ +#define E1000_ICH_FWSM_FW_VALID 0x00008000 #define E1000_ICH_MNG_IAMT_MODE 0x2 @@ -260,6 +262,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; + u32 ctrl; s32 ret_val = 0; phy->addr = 1; @@ -274,6 +277,23 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked; phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { + /* + * The MAC-PHY interconnect may still be in SMBus mode + * after Sx->S0. Toggle the LANPHYPC Value bit to force + * the interconnect to PCIe mode, but only if there is no + * firmware present otherwise firmware will have done it. + */ + ctrl = er32(CTRL); + ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; + ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; + ew32(CTRL, ctrl); + e1e_flush(); + udelay(10); + ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; + ew32(CTRL, ctrl); + msleep(50); + } /* * Reset the PHY before any acccess to it. Doing so, ensures that * the PHY is in a known good state before we read/write PHY registers.