From patchwork Tue Oct 21 08:53:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 401362 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 53999140077 for ; Tue, 21 Oct 2014 19:54:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754730AbaJUIyN (ORCPT ); Tue, 21 Oct 2014 04:54:13 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:64498 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754615AbaJUIyC (ORCPT ); Tue, 21 Oct 2014 04:54:02 -0400 Received: by mail-wi0-f170.google.com with SMTP id hi2so10381080wib.3 for ; Tue, 21 Oct 2014 01:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; bh=gYM2dbhd6fMVqQjMXJ/oOXOo+s5iftXlZooa2YGykEk=; b=eeZhLZB+tdvmukkwcabk+nenKSgXtkXtWgVKH372tzWlLZcaNMw7O83HhmduAQWSsr L063wxqXKs9aqU3Dek3O0nkkPOZ0bEsGESUSQSkCzzMTtmo2DQD+tsS5Xl0NxOXXC8SX 9GPwSTVRKxNOxNI8v5IGFhDuAhdqTQ9iNFkf66j5h299cWoNp2iVZvyGxr1IS8OHm8Yp IoHOWUvxC1NrvSBdki/i6y/ElmLS+0+oKBGVxP5hUXd1v/O7KHHXAjZICfjUASUwVFpw r5IvMu7kaOaYIalbYAhKGpoSvZff2zYjbXHcbEcnFs9u/C9pKrMquakGFcgHWQtuf0Ly /lVw== X-Received: by 10.194.90.144 with SMTP id bw16mr2073386wjb.133.1413881640144; Tue, 21 Oct 2014 01:54:00 -0700 (PDT) Received: from topkick.lan (f052063137.adsl.alicedsl.de. [78.52.63.137]) by mx.google.com with ESMTPSA id fm10sm12351711wib.21.2014.10.21.01.53.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Oct 2014 01:53:59 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Cc: "David S. Miller" , =?UTF-8?q?Antoine=20T=C3=A9nart?= , Florian Fainelli , Eric Miao , Haojian Zhuang , linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/9] ARM: berlin: Add BG2 ethernet DT nodes Date: Tue, 21 Oct 2014 10:53:44 +0200 Message-Id: <1413881627-21639-7-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1413881627-21639-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1413881627-21639-1-git-send-email-sebastian.hesselbarth@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Marvell BG2 has two fast ethernet controllers with internal PHY, add the corresponding nodes to SoC dtsi. Tested-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- Cc: "David S. Miller" Cc: "Antoine Ténart" Cc: Florian Fainelli Cc: Eric Miao Cc: Haojian Zhuang Cc: linux-arm-kernel@lists.infradead.org Cc: netdev@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- arch/arm/boot/dts/berlin2.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 9d7c810ebd0b..31d5922263d7 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -79,11 +79,47 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + phy-connection-type = "mii"; + reg = <0>; + }; + }; + cpu-ctrl@dd0000 { compatible = "marvell,berlin-cpu-ctrl"; reg = <0xdd0000 0x10000>; }; + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = ; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + phy-connection-type = "mii"; + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>;