From patchwork Fri Jul 18 18:28:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zi Shen Lim X-Patchwork-Id: 371687 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 239FE140132 for ; Sat, 19 Jul 2014 04:30:08 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946028AbaGRS2v (ORCPT ); Fri, 18 Jul 2014 14:28:51 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:36715 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1945999AbaGRS2t (ORCPT ); Fri, 18 Jul 2014 14:28:49 -0400 Received: by mail-pd0-f170.google.com with SMTP id g10so5511701pdj.29 for ; Fri, 18 Jul 2014 11:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B1MtGTRIX+9Q2AmWc5UVXQuHyloEfy723vLp0FEq4i0=; b=ckjXeaPMW+37AuDvbt/2gVkN02DhmRpgu5vWs04DjF1ZehDSoVDBTtjtEspHQ3n6+f P3i9ONID7EwwkRntdSIKEgXGt591sefiBJnsfUp25r2uyVijUOyanNrjmiBnLgoLV9jc Aj4g+1mcGjzIae3/0A8Yv0FPnsuBh8lXrMdN3rLfOoCzM9VImhcU8LUY+9kh481m4JXz OlsWemdbOuFSMOPvR0NTzzxdfaJrpLm9NBmsDnJ+RITPWtkAuOhtukVc3HurxmW5FhaN 7wT/N7yPfvAJNEDWtdWFbaJh+hYqHkAwTdQ82o1AB0aBF5cILJ9b9RZ0qg4Cg2jYomQ1 /HEA== X-Received: by 10.66.66.108 with SMTP id e12mr7512701pat.35.1405708128880; Fri, 18 Jul 2014 11:28:48 -0700 (PDT) Received: from gup76.sbx05686.santaca.wayport.net (ip-64-134-230-66.public.wayport.net. [64.134.230.66]) by mx.google.com with ESMTPSA id og2sm8353017pdb.42.2014.07.18.11.28.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jul 2014 11:28:48 -0700 (PDT) From: Zi Shen Lim To: Catalin Marinas , Will Deacon , Jiang Liu , AKASHI Takahiro , "David S. Miller" , Daniel Borkmann , Alexei Starovoitov Cc: Zi Shen Lim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org Subject: [PATCH 11/14] arm64: introduce aarch64_insn_gen_data2() Date: Fri, 18 Jul 2014 11:28:17 -0700 Message-Id: <1405708100-13604-12-git-send-email-zlim.lnx@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1405708100-13604-1-git-send-email-zlim.lnx@gmail.com> References: <1405708100-13604-1-git-send-email-zlim.lnx@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Introduce function to generate data-processing (2 source) instructions. Signed-off-by: Zi Shen Lim --- arch/arm64/include/asm/insn.h | 20 ++++++++++++++++++ arch/arm64/kernel/insn.c | 48 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 246d214..367245f 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -191,6 +191,15 @@ enum aarch64_insn_data1_type { AARCH64_INSN_DATA1_REVERSE_64, }; +enum aarch64_insn_data2_type { + AARCH64_INSN_DATA2_UDIV, + AARCH64_INSN_DATA2_SDIV, + AARCH64_INSN_DATA2_LSLV, + AARCH64_INSN_DATA2_LSRV, + AARCH64_INSN_DATA2_ASRV, + AARCH64_INSN_DATA2_RORV, +}; + #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ { return (code & (mask)) == (val); } \ @@ -217,6 +226,12 @@ __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000) __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000) __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000) __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000) +__AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800) +__AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00) +__AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000) +__AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400) +__AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800) +__AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00) __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400) __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800) __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00) @@ -289,6 +304,11 @@ u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst, enum aarch64_insn_register src, enum aarch64_insn_variant variant, enum aarch64_insn_data1_type type); +u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst, + enum aarch64_insn_register src, + enum aarch64_insn_register reg, + enum aarch64_insn_variant variant, + enum aarch64_insn_data2_type type); bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 81ef3b5..c054164 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -784,3 +784,51 @@ u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst, return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src); } + +u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst, + enum aarch64_insn_register src, + enum aarch64_insn_register reg, + enum aarch64_insn_variant variant, + enum aarch64_insn_data2_type type) +{ + u32 insn; + + switch (type) { + case AARCH64_INSN_DATA2_UDIV: + insn = aarch64_insn_get_udiv_value(); + break; + case AARCH64_INSN_DATA2_SDIV: + insn = aarch64_insn_get_sdiv_value(); + break; + case AARCH64_INSN_DATA2_LSLV: + insn = aarch64_insn_get_lslv_value(); + break; + case AARCH64_INSN_DATA2_LSRV: + insn = aarch64_insn_get_lsrv_value(); + break; + case AARCH64_INSN_DATA2_ASRV: + insn = aarch64_insn_get_asrv_value(); + break; + case AARCH64_INSN_DATA2_RORV: + insn = aarch64_insn_get_rorv_value(); + break; + default: + BUG_ON(1); + } + + switch (variant) { + case AARCH64_INSN_VARIANT_32BIT: + break; + case AARCH64_INSN_VARIANT_64BIT: + insn |= AARCH64_INSN_SF_BIT; + break; + default: + BUG_ON(1); + } + + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst); + + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src); + + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg); +}