From patchwork Fri Jul 11 07:35:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varka Bhadram X-Patchwork-Id: 369025 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A34771400A8 for ; Fri, 11 Jul 2014 17:37:32 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753098AbaGKHhE (ORCPT ); Fri, 11 Jul 2014 03:37:04 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:42204 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752961AbaGKHhB (ORCPT ); Fri, 11 Jul 2014 03:37:01 -0400 Received: by mail-pa0-f46.google.com with SMTP id eu11so999144pac.33 for ; Fri, 11 Jul 2014 00:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eTIHfon5AH+avdGgZDOa5xHHUjVI81SEbalAReB0e2Q=; b=AdXNMy51HlvwnEpEqHpojfcUusOEMqEBtRuRXjanMN48ttbenFY8rftARhdDEce9aR aXWCldMNnw8buDZ0wVG0B6KHBFia9kcVm/4d9iPlh0DvAhziZyg2kqT9TJQK+N5fxMpy O4FDxy/UM0Nf3/GtyvArXRb5gFpi+AIUHdPQfWOF8qTdixc+Yf4tfe7jgX+HauUIwCKN /7ST6RjIHYA+NIcO+5u5c0PXSHbASIZA302i+jit8O2I8CUfKQrLCzzwfZLztz4RnHnG 2GLfcK4eOEVGYNm85cuF1uAfQepeVUpGAVNlycMZ57g5aZhT9GiS1gorRwh87kgiGeVx uxmA== X-Received: by 10.70.34.39 with SMTP id w7mr22386972pdi.19.1405064220970; Fri, 11 Jul 2014 00:37:00 -0700 (PDT) Received: from cdac.hyderabad.cdac.in ([196.12.45.164]) by mx.google.com with ESMTPSA id v5sm1902490pdc.7.2014.07.11.00.36.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 11 Jul 2014 00:37:00 -0700 (PDT) From: varkabhadram@gmail.com To: netdev@vger.kernel.org Cc: Thomas.Lendacky@amd.com, geert+renesas@linux-m68k.org, ebiederm@xmission.com, macro@linux-mips.org, linux-kernel@vger.kernel.org, davem@davemloft.net, Varka Bhadram Subject: [PATCH net-next 8/8] ethernet: amd: switch case fixes Date: Fri, 11 Jul 2014 13:05:10 +0530 Message-Id: <1405064110-22579-9-git-send-email-varkabhadram@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405064110-22579-1-git-send-email-varkabhadram@gmail.com> References: <1405064110-22579-1-git-send-email-varkabhadram@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Varka Bhadram This patch fix the *swith* case indentation and usage issues Signed-off-by: Varka Bhadram --- drivers/net/ethernet/amd/amd8111e.c | 117 +++++++++++++++++------------------ 1 file changed, 58 insertions(+), 59 deletions(-) diff --git a/drivers/net/ethernet/amd/amd8111e.c b/drivers/net/ethernet/amd/amd8111e.c index f0d3809..ab2e09b9 100644 --- a/drivers/net/ethernet/amd/amd8111e.c +++ b/drivers/net/ethernet/amd/amd8111e.c @@ -197,23 +197,24 @@ static void amd8111e_set_ext_phy(struct net_device *dev) advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE); tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); switch (lp->ext_phy_option) { - default: - case SPEED_AUTONEG: /* advertise all values */ - tmp |= (ADVERTISE_10HALF | ADVERTISE_10FULL | - ADVERTISE_100HALF | ADVERTISE_100FULL); - break; - case SPEED10_HALF: - tmp |= ADVERTISE_10HALF; - break; - case SPEED10_FULL: - tmp |= ADVERTISE_10FULL; - break; - case SPEED100_HALF: - tmp |= ADVERTISE_100HALF; - break; - case SPEED100_FULL: - tmp |= ADVERTISE_100FULL; - break; + case SPEED_AUTONEG: /* advertise all values */ + tmp |= (ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL); + break; + case SPEED10_HALF: + tmp |= ADVERTISE_10HALF; + break; + case SPEED10_FULL: + tmp |= ADVERTISE_10FULL; + break; + case SPEED100_HALF: + tmp |= ADVERTISE_100HALF; + break; + case SPEED100_FULL: + tmp |= ADVERTISE_100FULL; + break; + default: + break; } if (advert != tmp) @@ -383,49 +384,47 @@ static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod) void __iomem *mmio = lp->mmio; struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf; + switch (cmod) { + case RX_INTR_COAL: + timeout = coal_conf->rx_timeout; + event_count = coal_conf->rx_event_count; + if (timeout > MAX_TIMEOUT || + event_count > MAX_EVENT_COUNT) + return -EINVAL; + + timeout = timeout * DELAY_TIMER_CONV; + writel(VAL0 | STINTEN, mmio + INTEN0); + writel((u32)DLY_INT_A_R0 | (event_count << 16) | + timeout, mmio+DLY_INT_A); + break; - switch (cmod) - { - case RX_INTR_COAL: - timeout = coal_conf->rx_timeout; - event_count = coal_conf->rx_event_count; - if (timeout > MAX_TIMEOUT || - event_count > MAX_EVENT_COUNT) - return -EINVAL; - - timeout = timeout * DELAY_TIMER_CONV; - writel(VAL0 | STINTEN, mmio + INTEN0); - writel((u32)DLY_INT_A_R0 | (event_count << 16) | - timeout, mmio+DLY_INT_A); - break; - - case TX_INTR_COAL: - timeout = coal_conf->tx_timeout; - event_count = coal_conf->tx_event_count; - if (timeout > MAX_TIMEOUT || - event_count > MAX_EVENT_COUNT) - return -EINVAL; - - - timeout = timeout * DELAY_TIMER_CONV; - writel(VAL0 | STINTEN, mmio + INTEN0); - writel((u32)DLY_INT_B_T0 | (event_count << 16) | - timeout, mmio + DLY_INT_B); - break; - - case DISABLE_COAL: - writel(0, mmio + STVAL); - writel(STINTEN, mmio + INTEN0); - writel(0, mmio + DLY_INT_B); - writel(0, mmio + DLY_INT_A); - break; - case ENABLE_COAL: - /* Start the timer (0.5 sec) */ - writel((u32)SOFT_TIMER_FREQ, mmio + STVAL); - writel(VAL0 | STINTEN, mmio + INTEN0); - break; - default: - break; + case TX_INTR_COAL: + timeout = coal_conf->tx_timeout; + event_count = coal_conf->tx_event_count; + if (timeout > MAX_TIMEOUT || + event_count > MAX_EVENT_COUNT) + return -EINVAL; + + timeout = timeout * DELAY_TIMER_CONV; + writel(VAL0 | STINTEN, mmio + INTEN0); + writel((u32)DLY_INT_B_T0 | (event_count << 16) | + timeout, mmio + DLY_INT_B); + break; + + case DISABLE_COAL: + writel(0, mmio + STVAL); + writel(STINTEN, mmio + INTEN0); + writel(0, mmio + DLY_INT_B); + writel(0, mmio + DLY_INT_A); + break; + + case ENABLE_COAL: + /* Start the timer (0.5 sec) */ + writel((u32)SOFT_TIMER_FREQ, mmio + STVAL); + writel(VAL0 | STINTEN, mmio + INTEN0); + break; + default: + break; } return 0;