From patchwork Wed Mar 19 22:15:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 331903 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 034A92C009A for ; Thu, 20 Mar 2014 09:15:58 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758167AbaCSWP3 (ORCPT ); Wed, 19 Mar 2014 18:15:29 -0400 Received: from quartz.orcorp.ca ([184.70.90.242]:35863 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757960AbaCSWP0 (ORCPT ); Wed, 19 Mar 2014 18:15:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=obsidianresearch.com; s=rsa1; h=Message-Id:Date:Subject:Cc:To:From; bh=bU2eDatnLzH9jI/ukPy39aTdJBjYGT/XQW1MaPcO3q8=; b=2i5NyDzv7YngInQ6KLupFjYCBpTNjnE6R9CqZsVS620SgJWyaEc7eLAArYX/oWlTvK9rIPBwNrGzu+ZDaURTclo0FuBo+ucyWiG/tV9J31tUUL6FQ5LVvuki7Lvya+UFYhn/MSOzOxnPGiyTiSmJDTJzEWacdskZgFUYiwwpKj4=; Received: from [10.0.0.161] (helo=jggl.edm.orcorp.ca) by quartz.orcorp.ca with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1WQOlh-00068L-HJ; Wed, 19 Mar 2014 16:15:25 -0600 From: Jason Gunthorpe To: "David S. Miller" Cc: Rob Herring , Florian Fainelli , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v2a 1/2] dt: Document a compatible entry for MDIO ethernet Phys Date: Wed, 19 Mar 2014 16:15:23 -0600 Message-Id: <1395267324-5788-1-git-send-email-jgunthorpe@obsidianresearch.com> X-Mailer: git-send-email 1.8.1.2 X-Broken-Reverse-DNS: no host name found for IP address 10.0.0.161 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This describes a compatible entry of the form: ethernet-phy-idAAAA,BBBB Which is modelled after the PCI structured compatible entry (pciVVVV,DDDD.SSSS.ssss.RR) If present the OF core will be able to use this information to directly create the correct phy without auto probing the bus. Signed-off-by: Jason Gunthorpe Acked-by: Rob Herring Acked-by: Florian Fainelli --- Documentation/devicetree/bindings/net/phy.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) - Resend for net-next diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 58307d0..5b8c589 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt @@ -21,10 +21,18 @@ Optional Properties: elements. - max-speed: Maximum PHY supported speed (10, 100, 1000...) + If the phy's identifier is known then the list may contain an entry + of the form: "ethernet-phy-idAAAA.BBBB" where + AAAA - The value of the 16 bit Phy Identifier 1 register as + 4 hex digits. This is the chip vendor OUI bits 3:18 + BBBB - The value of the 16 bit Phy Identifier 2 register as + 4 hex digits. This is the chip vendor OUI bits 19:24, + followed by 10 bits of a vendor specific ID. + Example: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22"; interrupt-parent = <40000>; interrupts = <35 1>; reg = <0>;