From patchwork Wed Sep 11 18:22:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 274349 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 02E8F2C027A for ; Thu, 12 Sep 2013 04:21:36 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755461Ab3IKSV3 (ORCPT ); Wed, 11 Sep 2013 14:21:29 -0400 Received: from mail-pb0-f48.google.com ([209.85.160.48]:55251 "EHLO mail-pb0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754070Ab3IKSV2 (ORCPT ); Wed, 11 Sep 2013 14:21:28 -0400 Received: by mail-pb0-f48.google.com with SMTP id ma3so9362970pbc.21 for ; Wed, 11 Sep 2013 11:21:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rO5vX/C/MLZnJyz3DiJCtQwADNH9HDyyMqHrsc/S+IA=; b=AMT2r0GVoNq4Onhco+k4oBdvw/bq36ChhL00XyXYB18QmBWPiqbc7x4SX/+658KEnj S2Ig+qiHDHGydNfRVV0oCs1hhWv5yGORCzCD6HVigXgUp1zoePFSXHRGEWqdJrDSEsyo Ev3HlpWSZPUHrkKzPDySw/zUlBUG2Rh7aNU0TvKvEa/Zce9Fqew3frsfmmeBBym6DG7a YLfiTGq1shuurSdU53Q3i7yX5By6p12Xi7gBXE8NSf8wjurlhFYt91bHVl7pnTiTvdAP aVVs6Zx9kUQKo3ZJzQ9DIxqgSrzMpjpo/fJ5GdfNkjozcBLaLfVB7i4BTlZgeqBlYsxm CY9w== X-Gm-Message-State: ALoCoQkzl5dcpIm12zum0vSxvxqS8pHMH2dP2djb3fIlxkUcDvm76FeCxvqnkSnGqyK5Tb3DzTDD X-Received: by 10.66.192.132 with SMTP id hg4mr5293914pac.84.1378923688192; Wed, 11 Sep 2013 11:21:28 -0700 (PDT) Received: from scylla ([184.101.98.226]) by mx.google.com with ESMTPSA id go4sm27481320pbb.15.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 11 Sep 2013 11:21:27 -0700 (PDT) Received: by scylla (sSMTP sendmail emulation); Wed, 11 Sep 2013 11:22:45 -0700 From: Jon Mason To: netdev@vger.kernel.org Cc: Nithin Nayak Sujir , Michael Chan Subject: [PATCH 2/2] tg3: Use pci_dev pm_cap Date: Wed, 11 Sep 2013 11:22:40 -0700 Message-Id: <1378923760-16232-2-git-send-email-jdmason@kudzu.us> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1378923760-16232-1-git-send-email-jdmason@kudzu.us> References: <1378923760-16232-1-git-send-email-jdmason@kudzu.us> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Use the already existing pm_cap variable in struct pci_dev for determining the power management offset. This saves the driver from having to keep track of an extra variable. Signed-off-by: Jon Mason Cc: Nithin Nayak Sujir Cc: Michael Chan --- drivers/net/ethernet/broadcom/tg3.c | 5 ++--- drivers/net/ethernet/broadcom/tg3.h | 1 - 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 5701f3d..938e05c 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -16192,12 +16192,12 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) * So explicitly force the chip into D0 here. */ pci_read_config_dword(tp->pdev, - tp->pm_cap + PCI_PM_CTRL, + tp->pdev->pm_cap + PCI_PM_CTRL, &pm_reg); pm_reg &= ~PCI_PM_CTRL_STATE_MASK; pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; pci_write_config_dword(tp->pdev, - tp->pm_cap + PCI_PM_CTRL, + tp->pdev->pm_cap + PCI_PM_CTRL, pm_reg); /* Also, force SERR#/PERR# in PCI command. */ @@ -17346,7 +17346,6 @@ static int tg3_init_one(struct pci_dev *pdev, tp = netdev_priv(dev); tp->pdev = pdev; tp->dev = dev; - tp->pm_cap = pdev->pm_cap; tp->rx_mode = TG3_DEF_RX_MODE; tp->tx_mode = TG3_DEF_TX_MODE; tp->irq_sync = 1; diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index ddb8be1..7025780 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -3234,7 +3234,6 @@ struct tg3 { u8 pci_lat_timer; int pci_fn; - int pm_cap; int msi_cap; int pcix_cap; int pcie_readrq;