From patchwork Fri Mar 22 17:33:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 230189 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 971A82C00C3 for ; Sat, 23 Mar 2013 04:34:02 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161100Ab3CVRdw (ORCPT ); Fri, 22 Mar 2013 13:33:52 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:37963 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161061Ab3CVRdv (ORCPT ); Fri, 22 Mar 2013 13:33:51 -0400 Received: from dude.hi.pengutronix.de ([2001:6f8:1178:2:21e:67ff:fe11:9c5c]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1UJ5qg-0003ps-Ri; Fri, 22 Mar 2013 18:33:50 +0100 Received: from str by dude.hi.pengutronix.de with local (Exim 4.80) (envelope-from ) id 1UJ5qg-0004fd-6c; Fri, 22 Mar 2013 18:33:50 +0100 From: Steffen Trumtrar To: netdev@vger.kernel.org Cc: Steffen Trumtrar , Nicolas Ferre Subject: [PATCH 2/3] net/macb: force endian_swp_pkt_en to off Date: Fri, 22 Mar 2013 18:33:34 +0100 Message-Id: <1363973615-17863-2-git-send-email-s.trumtrar@pengutronix.de> X-Mailer: git-send-email 1.8.2.rc2 In-Reply-To: <1363973615-17863-1-git-send-email-s.trumtrar@pengutronix.de> References: <1363973615-17863-1-git-send-email-s.trumtrar@pengutronix.de> X-SA-Exim-Connect-IP: 2001:6f8:1178:2:21e:67ff:fe11:9c5c X-SA-Exim-Mail-From: str@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The core has a bit for swapping packet data endianism. Reset default from Cadence is off. Xilinx however, who uses this core on the Zynq SoCs, opted for on. Force it to off. This shouldn't change the behaviour for current users of the macb, but enables usage on Zynq devices. Signed-off-by: Steffen Trumtrar Cc: Nicolas Ferre --- drivers/net/ethernet/cadence/macb.c | 1 + drivers/net/ethernet/cadence/macb.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index 817835e..71e766b 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1057,6 +1057,7 @@ static void macb_configure_dma(struct macb *bp) dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); dmacfg |= GEM_BF(FBLDO, 16); dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); + dmacfg &= ~GEM_BIT(ENDIA); gem_writel(bp, DMACFG, dmacfg); } } diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 570908b..993d703 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -173,6 +173,8 @@ /* Bitfields in DMACFG. */ #define GEM_FBLDO_OFFSET 0 #define GEM_FBLDO_SIZE 5 +#define GEM_ENDIA_OFFSET 7 +#define GEM_ENDIA_SIZE 1 #define GEM_RXBMS_OFFSET 8 #define GEM_RXBMS_SIZE 2 #define GEM_TXPBMS_OFFSET 10