From patchwork Thu Oct 13 14:37:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Fleming X-Patchwork-Id: 119545 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id ACA44B6F94 for ; Fri, 14 Oct 2011 01:38:29 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755865Ab1JMOiZ (ORCPT ); Thu, 13 Oct 2011 10:38:25 -0400 Received: from am1ehsobe003.messaging.microsoft.com ([213.199.154.206]:58812 "EHLO AM1EHSOBE003.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755481Ab1JMOiY (ORCPT ); Thu, 13 Oct 2011 10:38:24 -0400 Received: from mail55-am1-R.bigfish.com (10.3.201.240) by AM1EHSOBE003.bigfish.com (10.3.204.23) with Microsoft SMTP Server id 14.1.225.22; Thu, 13 Oct 2011 14:38:23 +0000 Received: from mail55-am1 (localhost.localdomain [127.0.0.1]) by mail55-am1-R.bigfish.com (Postfix) with ESMTP id 0037E1AC8411; Thu, 13 Oct 2011 14:38:23 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 0, Received: from mail55-am1 (localhost.localdomain [127.0.0.1]) by mail55-am1 (MessageSwitch) id 131851666552292_28948; Thu, 13 Oct 2011 14:37:45 +0000 (UTC) Received: from AM1EHSMHS008.bigfish.com (unknown [10.3.201.253]) by mail55-am1.bigfish.com (Postfix) with ESMTP id EA44E898054; Thu, 13 Oct 2011 14:37:44 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS008.bigfish.com (10.3.207.108) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 13 Oct 2011 14:37:44 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Thu, 13 Oct 2011 09:37:42 -0500 Received: from localhost (right.am.freescale.net [10.82.193.13]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p9DEbfGi009886; Thu, 13 Oct 2011 09:37:41 -0500 (CDT) From: Andy Fleming To: CC: Subject: [PATCH v3 2/3] phylib: Convert MDIO bitbang to new MDIO 45 format Date: Thu, 13 Oct 2011 09:37:39 -0500 Message-ID: <1318516660-25452-3-git-send-email-afleming@freescale.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1318516660-25452-1-git-send-email-afleming@freescale.com> References: <1318516660-25452-1-git-send-email-afleming@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Now that we've added somewhat more complete MDIO 45 support to the PHY Lib, convert the MDIO bitbang driver to use this new infrastructure. Signed-off-by: Andy Fleming --- v2: rebase on top of tree v3: Make patch series more coherent drivers/net/phy/mdio-bitbang.c | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/mdio-bitbang.c b/drivers/net/phy/mdio-bitbang.c index 2f6f02e..df7f496 100644 --- a/drivers/net/phy/mdio-bitbang.c +++ b/drivers/net/phy/mdio-bitbang.c @@ -134,11 +134,10 @@ static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg) MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices can exist on the same bus. Normal devices should ignore the MDIO_ADDR phase. */ -static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) +static void mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, int devad, + int reg) { - unsigned int dev_addr = (addr >> 16) & 0x1F; - unsigned int reg = addr & 0xFFFF; - mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr); + mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, devad); /* send the turnaround (10) */ mdiobb_send_bit(ctrl, 1); @@ -148,8 +147,6 @@ static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_get_bit(ctrl); - - return dev_addr; } static int mdiobb_read(struct mii_bus *bus, int phy, int devad, int reg) @@ -157,11 +154,13 @@ static int mdiobb_read(struct mii_bus *bus, int phy, int devad, int reg) struct mdiobb_ctrl *ctrl = bus->priv; int ret, i; - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); - } else + /* Clause 22 PHYs don't have a devad */ + if (devad == MDIO_DEVAD_NONE) mdiobb_cmd(ctrl, MDIO_READ, phy, reg); + else { + mdiobb_cmd_addr(ctrl, phy, devad, reg); + mdiobb_cmd(ctrl, MDIO_C45_READ, phy, devad); + } ctrl->ops->set_mdio_dir(ctrl, 0); @@ -186,11 +185,13 @@ static int mdiobb_write(struct mii_bus *bus, int phy, int devad, int reg, { struct mdiobb_ctrl *ctrl = bus->priv; - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); - } else + /* Clause 22 PHYs don't have a devad */ + if (devad == MDIO_DEVAD_NONE) mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg); + else { + mdiobb_cmd_addr(ctrl, phy, devad, reg); + mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, devad); + } /* send the turnaround (10) */ mdiobb_send_bit(ctrl, 1);