From patchwork Fri May 21 18:31:51 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Fleming X-Patchwork-Id: 53204 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3DE56B7D29 for ; Sat, 22 May 2010 04:32:11 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934201Ab0EUSb6 (ORCPT ); Fri, 21 May 2010 14:31:58 -0400 Received: from az33egw02.freescale.net ([192.88.158.103]:32900 "EHLO az33egw02.freescale.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934101Ab0EUSb4 (ORCPT ); Fri, 21 May 2010 14:31:56 -0400 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by az33egw02.freescale.net (8.14.3/az33egw02) with ESMTP id o4LIVt1w026420; Fri, 21 May 2010 11:31:55 -0700 (MST) Received: from localhost (firefly.am.freescale.net [10.82.123.6]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id o4LIexT6014263; Fri, 21 May 2010 13:40:59 -0500 (CDT) From: Andy Fleming To: davem@davemloft.net Cc: netdev@vger.kernel.org Subject: [PATCH v2 2/2] phylib: Convert MDIO bitbang to new MDIO 45 format Date: Fri, 21 May 2010 13:31:51 -0500 Message-Id: <1274466711-24962-3-git-send-email-afleming@freescale.com> X-Mailer: git-send-email 1.6.5.2.g6ff9a In-Reply-To: <1274466711-24962-2-git-send-email-afleming@freescale.com> References: <1274466711-24962-1-git-send-email-afleming@freescale.com> <1274466711-24962-2-git-send-email-afleming@freescale.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Now that we've added somewhat more complete MDIO 45 support to the PHY Lib, convert the MDIO bitbang driver to use this new infrastructure. Signed-off-by: Andy Fleming --- drivers/net/phy/mdio-bitbang.c | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/mdio-bitbang.c b/drivers/net/phy/mdio-bitbang.c index 2f6f02e..be7ae74 100644 --- a/drivers/net/phy/mdio-bitbang.c +++ b/drivers/net/phy/mdio-bitbang.c @@ -134,11 +134,10 @@ static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg) MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices can exist on the same bus. Normal devices should ignore the MDIO_ADDR phase. */ -static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) +static void mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, int devad, + int reg) { - unsigned int dev_addr = (addr >> 16) & 0x1F; - unsigned int reg = addr & 0xFFFF; - mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr); + mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, devad); /* send the turnaround (10) */ mdiobb_send_bit(ctrl, 1); @@ -148,8 +147,6 @@ static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_get_bit(ctrl); - - return dev_addr; } static int mdiobb_read(struct mii_bus *bus, int phy, int devad, int reg) @@ -157,11 +154,13 @@ static int mdiobb_read(struct mii_bus *bus, int phy, int devad, int reg) struct mdiobb_ctrl *ctrl = bus->priv; int ret, i; - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); - } else + /* Clause 22 PHYs only use devad = 0, and Clause 45 only use nonzero */ + if (devad == MDIO_DEVAD_NONE) mdiobb_cmd(ctrl, MDIO_READ, phy, reg); + else { + mdiobb_cmd_addr(ctrl, phy, devad, reg); + mdiobb_cmd(ctrl, MDIO_C45_READ, phy, devad); + } ctrl->ops->set_mdio_dir(ctrl, 0); @@ -186,11 +185,13 @@ static int mdiobb_write(struct mii_bus *bus, int phy, int devad, int reg, { struct mdiobb_ctrl *ctrl = bus->priv; - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); - } else + /* Clause 22 PHYs only use devad = 0, and Clause 45 only use nonzero */ + if (devad == MDIO_DEVAD_NONE) mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg); + else { + mdiobb_cmd_addr(ctrl, phy, devad, reg); + mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, devad); + } /* send the turnaround (10) */ mdiobb_send_bit(ctrl, 1);