From patchwork Sat Mar 24 20:04:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 890525 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cogentembedded.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="h5h2T2IQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 407s0n6Shqz9s1l for ; Sun, 25 Mar 2018 07:08:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753498AbeCXUIM (ORCPT ); Sat, 24 Mar 2018 16:08:12 -0400 Received: from mail-lf0-f51.google.com ([209.85.215.51]:47049 "EHLO mail-lf0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752778AbeCXUE4 (ORCPT ); Sat, 24 Mar 2018 16:04:56 -0400 Received: by mail-lf0-f51.google.com with SMTP id j68-v6so22858707lfg.13 for ; Sat, 24 Mar 2018 13:04:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:organization:message-id:date:user-agent :mime-version:content-language:content-transfer-encoding; bh=ah3FJigGm3C4mwHdeTm0s4nS1ScWbMGgmN30yvr7Mj0=; b=h5h2T2IQYlDrYdeMT1xMWY0rWnLlX9kLk9EZJfp4PkrjkmoSpNmZkTBqwtf5YpyWdY X1EZrkQmTINpgRNAAgliylpVOYw21DqXVLnPIIGcglb5/tZxXYC7uZ0tYHcgMlrMeQVo A5cfB7KIyHGEfNJBLGfQgMhk3EPGrlbMN6gAQNi5h+vcDfX8jt0mLg0m5XKlrhQnUL3e sGd1BjiaKKgRY5gYqiobrisGLiAKsYdTLcUuJvuq7oGLdPiNNILjsFbVkQ0ROvvDlbFG 85sWFhbErPbFsEVUe2po2AfBpBfJ71PNLiWDIVFDiZPoxwX1kgBclFuHUAqGO1BX3Phb aGSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:organization:message-id:date :user-agent:mime-version:content-language:content-transfer-encoding; bh=ah3FJigGm3C4mwHdeTm0s4nS1ScWbMGgmN30yvr7Mj0=; b=SvTvtzJTzAJe2lax7gCGN2op/PieYJ1CRxOZCyaucE5zIF26wm4AYf/mAis/MWO2li e7NbrMkffCY/BUWjkHlf2nEvEN1RJHlTkoZ7j7xOBcytbitjRkPM6ZiKHxlfOgYCWJ1Y Fcwmcxe/owKqtWw+gRwBbF2Gm8MhSsGPRPHxrswSsn0Y9OpsGvzGU3/7e7t91RxxKqZL jztPlKuC+L2K0oXqlGlM/p1Pad9jChNlzxiZsvjtJFefX/3Xn/hK08W0VKGnLRgT2SID KnIGhekwWVL9MA/tQgnz+HhUA9RiMH1HymE1vnYseXzyKatpAFKx5QQyH2TUrMBWlUpK c2vw== X-Gm-Message-State: AElRT7FDXjN1EfoUaQkqVadVm3r+UsDaWdN0RO5WY2cTvigMZOcl1Nzs ebcgyhSGohXqbdW3ivRhFnJJk6sMrNg= X-Google-Smtp-Source: AG47ELt1QoLeGnYysKMWiXIs67Xzb5HhZco3UvA5DW3lNOXfQEezrEkRiY3/NiVWaytrUwy8wc9ZwA== X-Received: by 10.46.128.77 with SMTP id p13mr21899963ljg.56.1521921895197; Sat, 24 Mar 2018 13:04:55 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.80.64]) by smtp.gmail.com with ESMTPSA id o132-v6sm2949730lfe.91.2018.03.24.13.04.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Mar 2018 13:04:54 -0700 (PDT) From: Sergei Shtylyov Subject: [PATCH 0/2] sh_eth: unify the SoC feature checks To: netdev@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org Organization: Cogent Embedded Message-ID: Date: Sat, 24 Mar 2018 23:04:53 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 Content-Language: en-MW Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hello! Here's a set of 5 patches against DaveM's 'net-next.git' repo. The Ether driver sometimes uses the bit fields in 'struct sh_eth_cpu_data' to check which Ether registers exist in a certain SoC and sometimes it uses sh_eth_is_{gether|rz_fast_ether}() which basically compares 2 pointers (1 of them being constant) -- the latter is definitely not a strongest feature of the RISC CPUs (be it SH or ARM), so I decided to get rid of this type of the feature checks in favour of the bit fields (I've also made use of a 32-bit value and method pointer where appropriate)... [1/5] sh_eth: add sh_eth_cpu_data::soft_reset() method [2/5] sh_eth: add sh_eth_cpu_data::edtrr_trns value [3/5] sh_eth: add sh_eth_cpu_data::xdfar_rw flag [4/5] sh_eth: add sh_eth_cpu_data::no_tx_cntr flag [5/5] sh_eth: add sh_eth_cpu_data::cexcr flag MBR, Sergei