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Mon, 23 Nov 2020 17:42:46 +0000 Received: from MW2PR18MB2267.namprd18.prod.outlook.com ([fe80::e17f:37fb:4eb3:c703]) by MW2PR18MB2267.namprd18.prod.outlook.com ([fe80::e17f:37fb:4eb3:c703%4]) with mapi id 15.20.3564.039; Mon, 23 Nov 2020 17:42:46 +0000 From: Alex Belits To: "nitesh@redhat.com" , "frederic@kernel.org" CC: Prasun Kapoor , "linux-api@vger.kernel.org" , "davem@davemloft.net" , "trix@redhat.com" , "mingo@kernel.org" , "catalin.marinas@arm.com" , "rostedt@goodmis.org" , "linux-kernel@vger.kernel.org" , "peterx@redhat.com" , "tglx@linutronix.de" , "linux-arch@vger.kernel.org" , "mtosatti@redhat.com" , "will@kernel.org" , "peterz@infradead.org" , "leon@sidebranch.com" , "linux-arm-kernel@lists.infradead.org" , "pauld@redhat.com" , "netdev@vger.kernel.org" Subject: [PATCH v5 0/9] "Task_isolation" mode Thread-Topic: [PATCH v5 0/9] "Task_isolation" mode Thread-Index: AQHWwcAN4HMJq5rZb0WNk0YfmsaUgQ== Date: Mon, 23 Nov 2020 17:42:45 +0000 Message-ID: <8d887e59ca713726f4fcb25a316e1e932b02823e.camel@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: redhat.com; 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x-ms-exchange-antispam-messagedata: Crv+cFLHay9+M3Pg68PhaqvINHX/WL83jq/72lKlVPZS4Jzl00d1yfmFRGpkRIq2hTmFwztHv3bakBJpkiad9z2+ogTnYgwExK1u86NwgoJQOcOBPP3NmmbW8Q26NkzxprFsJl2PFV1EK9MX58Df1uDGTn3KUadKlMpFlCUDcb/48gIyHMwK9iyo8ejWvA60srJuyV2d2RJHIyAcSlcxivRqlAaL/CHUMZ4PS7zPjiAIlLURGqhN/hQmO/K+jiHAD7W1j0d0z8tEz5jc26gkHIUQ84qR8J7chkNDihr9tEubyo9ajAVi9ndSNMKsCxUNNMJdOUj1BA46iN5/DRlD06ahL7K5sJAfNX6t7iC8kAgZ4ij/GxWYM4CQiTubXNA7j17rk/JwDRw7PdPHR1IImkXPwVIiUJzT1UFlk30xVrfjROncOjGv083Y109VwF5fuckRZuYYMuf+xZpUzU3vHTPSsVj0MtiSwSC5QBnBbnmvv+jWuQv/eWrEPRdhFJ+utwROzvAAAwuCbVLxpVcKYprWjvFh4AsCyY/aCdrr8KbsBM6hrmsQkj4JLKhZjzi7iBxllIUJudDyehWGmVxcp177np7dO7qOqwUM+VpaoIUJg+yMb1nV9QfZyWBiPYV8xNFLHC3kqkft96uFB7350zplTlgIH+w+DgezuTimW+VWY+EHPpDxLPeV1fOWwZXT75b7VBxfwobrOi8QHWlC7DkCumW0HS8yEQUQIYcdaYnANBJCG+oUCTU+fHyLXs4aMIgGIg8M5QEG1vr/phStcU8SKuWLSBfNpk/yM7rqzrOLMKfvfWrfj73BoWWttQWAfNadsEVeNQNq6MJBhss6L8xZ+03yGp8tLXtcmy0yufd9ob5vECtHjlRUKqJJTyv0m9AQmNvUa9baeHO2Tr3rNg== Content-ID: <93B54AB342F93C4B9C188076FB9F6EC5@namprd18.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW2PR18MB2267.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a9d35cc7-fd55-4984-568f-08d88fd7302f X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Nov 2020 17:42:45.8256 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XOC/wgfjt+A22H0eumiI0/kRwya1nTdK/YNklTkp7JmvnWzsjF41XzZ/2QDfDijYMmXpCxG8IgJkFfjOv6bXGA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR18MB1342 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312,18.0.737 definitions=2020-11-23_17:2020-11-23,2020-11-23 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is an update of task isolation work that was originally done by Chris Metcalf and maintained by him until November 2017. It is adapted to the current kernel and cleaned up to implement its functionality in a more complete and cleaner manner. Previous version is at https://lore.kernel.org/netdev/04be044c1bcd76b7438b7563edc35383417f12c8.camel@marvell.com/ The last version by Chris Metcalf (now obsolete but may be relevant for comparison and understanding the origin of the changes) is at https://lore.kernel.org/lkml/1509728692-10460-1-git-send-email-cmetcalf@mellanox.com Supported architectures This version includes only architecture-independent code and arm64 support. x86 and arm support, and everything related to virtualization will be re-added later when new kernel entry/exit implementation will be accommodated. Support for other architectures can be added in a somewhat modular manner, however it heavily depends on the details of a kernel entry/exit support on any particular architecture. Development of common entry/exit and conversion to it should simplify that task. For now, this is the version that is currently being developed on arm64. Major changes since v4 The goal was to make isolation-breaking detection as generic as possible, and remove everything related to determining, _why_ isolation was broken. Originally reporting isolation breaking was done with a large number of of hooks in specific code (hardware interrupts, syscalls, IPIs, page faults, etc.), and it was necessary to cover all possible such events to have a reliable notification of a task about its isolation being broken. To avoid such a fragile mechanism, this version relies on mere fact of kernel being entered in isolation mode. As a result, reporting happens later in kernel code, however it covers everything. This means that now there is no specific reporting, in kernel log or elsewhere, about the reasons for breaking isolation. Information about that may be valuable at runtime, so a separate mechanism for generic reporting "why did CPU enter kernel" (with isolation or under other conditions) may be a good thing. That can be done later, however at this point it's important that task isolation does not require it, and such mechanism will not be developed with the limited purpose of supporting isolation alone. General description This is the result of development and maintenance of task isolation functionality that originally started based on task isolation patch v15 and was later updated to include v16. It provided predictable environment for userspace tasks running on arm64 processors alongside with full-featured Linux environment. It is intended to provide reliable interruption-free environment from the point when a userspace task enters isolation and until the moment it leaves isolation or receives a signal intentionally sent to it, and was successfully used for this purpose. While CPU isolation with nohz provides an environment that is close to this requirement, the remaining IPIs and other disturbances keep it from being usable for tasks that require complete predictability of CPU timing. This set of patches only covers the implementation of task isolation, however additional functionality, such as selective TLB flushes, may be implemented to avoid other kinds of disturbances that affect latency and performance of isolated tasks. The userspace support and test program is now at https://github.com/abelits/libtmc . It was originally developed for earlier implementation, so it has some checks that may be redundant now but kept for compatibility. My thanks to Chris Metcalf for design and maintenance of the original task isolation patch, Francis Giraldeau and Yuri Norov for various contributions to this work, Frederic Weisbecker for his work on CPU isolation and housekeeping that made possible to remove some less elegant solutions that I had to devise for earlier, <4.17 kernels, and Nitesh Narayan Lal for adapting earlier patches related to interrupt and work distribution in presence of CPU isolation.