From patchwork Wed Jul 1 21:34:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1320839 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=WX5JW3JU; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49xvdX6D3Rz9sRN for ; Thu, 2 Jul 2020 07:34:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727104AbgGAVey (ORCPT ); Wed, 1 Jul 2020 17:34:54 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:41349 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726144AbgGAVex (ORCPT ); Wed, 1 Jul 2020 17:34:53 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 8123B22EDB; Wed, 1 Jul 2020 23:34:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1593639291; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=T7aJavz2wzf4/442l8dNAV7MGO726zBOZq4cJ0+NXf8=; b=WX5JW3JUoUA5MWe3wbCNWxdMs/euVeFLuRWywCt+jx8xvKJyKTXO0Dg4YmOgajPxSapIKJ EIZEtOSRLUjvizdJdXpsXmvAeQZPxp6uQt5VLW4oANZZcu9mwEkUUCHAh+577rLdhPO2RN zzOX4qdT6RSeuk6vHpWRNiO/6ZeSWvY= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "David S . Miller" , Jakub Kicinski , Andrew Lunn , Michael Walle , Vladimir Oltean , Alex Marginean , Claudiu Manoil , Heiko Thiery , Russell King - ARM Linux admin Subject: [PATCH RESEND net-next v3 0/3] net: enetc: remove bootloader dependency Date: Wed, 1 Jul 2020 23:34:30 +0200 Message-Id: <20200701213433.9217-1-michael@walle.cc> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Spam: Yes Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is a resend of the series because the conversion to the phylink interface will likely take longer: https://lore.kernel.org/netdev/CA+h21hpBodyY8CtNH2ktRdc2FqPi=Fjp94=VVZvzSVbnvnfKVg@mail.gmail.com/ Unfortunately, we have boards in the wild with a bootloader which doesn't set the PCS up correctly. Thus I'd really see this patches picked up as an intermediate step until the phylink conversion is ready. Vladimir Oltean already offered to convert enetc to phylink when he converts the felix to phylink. After this series the PCS setup of the enetc looks almost the same as the current felix setup. Thus conversion should be easy. These patches were picked from the following series: https://lore.kernel.org/netdev/1567779344-30965-1-git-send-email-claudiu.manoil@nxp.com/ They have never been resent. I've picked them up, addressed Andrews comments, fixed some more bugs and asked Claudiu if I can keep their SOB tags; he agreed. I've tested this on our board which happens to have a bootloader which doesn't do the enetc setup in all cases. Though, only SGMII mode was tested. changes since v2: - removed SOBs from "net: enetc: Initialize SerDes for SGMII and USXGMII protocols" because almost everything has changed. - get a phy_device for the internal PCS PHY so we can use the phy_ functions instead of raw mdiobus writes - reuse macros already defined in fsl_mdio.h, move missing bits from felix to fsl_mdio.h, because they share the same PCS PHY building block - added 2500BaseX mode (based on felix init routine) - changed xgmii mode to usxgmii mode, because it is actually USXGMII and felix does the same. - fixed devad, which is 0x1f (MMD_VEND2) changes since v1: - mdiobus id is '"imdio-%s", dev_name(dev)' because the plain dev_name() is used by the emdio. - use mdiobus_write() instead of imdio->write(imdio, ..), since this is already a full featured mdiobus - set phy_mask to ~0 to avoid scanning the bus - use phy_interface_mode_is_rgmii(phy_mode) to also include the RGMII modes with pad delays. - move enetc_imdio_init() to enetc_pf.c, there shouldn't be any other users, should it? - renamed serdes to SerDes - printing the error code of mdiobus_register() in the error path - call mdiobus_unregister() on _remove() - call devm_mdiobus_free() if mdiobus_register() fails, since an error is not fatal Alex Marginean (1): net: enetc: Use DT protocol information to set up the ports Michael Walle (2): net: dsa: felix: move USXGMII defines to common place net: enetc: Initialize SerDes for SGMII and USXGMII protocols drivers/net/dsa/ocelot/felix_vsc9959.c | 21 -- .../net/ethernet/freescale/enetc/enetc_hw.h | 3 + .../net/ethernet/freescale/enetc/enetc_pf.c | 191 +++++++++++++++--- .../net/ethernet/freescale/enetc/enetc_pf.h | 5 + include/linux/fsl/enetc_mdio.h | 19 ++ 5 files changed, 194 insertions(+), 45 deletions(-)