Message ID | 20200528063847.27704-1-michael@walle.cc |
---|---|
Headers | show |
Series | net: enetc: remove bootloader dependency | expand |
Am 2020-05-28 08:38, schrieb Michael Walle: > These patches were picked from the following series: > https://lore.kernel.org/netdev/1567779344-30965-1-git-send-email-claudiu.manoil@nxp.com/ > They have never been resent. I've picked them up, addressed Andrews > comments, fixed some more bugs and asked Claudiu if I can keep their > SOB > tags; he agreed. I've tested this on our board which happens to have a > bootloader which doesn't do the enetc setup in all cases. Though, only > SGMII mode was tested. > > changes since v2: > - removed SOBs from "net: enetc: Initialize SerDes for SGMII and > USXGMII > protocols" because almost everything has changed. > - get a phy_device for the internal PCS PHY so we can use the phy_ > functions instead of raw mdiobus writes mhh after reading, https://lore.kernel.org/netdev/CA+h21hoq2qkmxDFEb2QgLfrbC0PYRBHsca=0cDcGOr3txy9hsg@mail.gmail.com/ this seems to be the wrong way of doing it. -michael
On Thu, 28 May 2020 at 11:18, Michael Walle <michael@walle.cc> wrote: > > Am 2020-05-28 08:38, schrieb Michael Walle: > > These patches were picked from the following series: > > https://lore.kernel.org/netdev/1567779344-30965-1-git-send-email-claudiu.manoil@nxp.com/ > > They have never been resent. I've picked them up, addressed Andrews > > comments, fixed some more bugs and asked Claudiu if I can keep their > > SOB > > tags; he agreed. I've tested this on our board which happens to have a > > bootloader which doesn't do the enetc setup in all cases. Though, only > > SGMII mode was tested. > > > > changes since v2: > > - removed SOBs from "net: enetc: Initialize SerDes for SGMII and > > USXGMII > > protocols" because almost everything has changed. > > - get a phy_device for the internal PCS PHY so we can use the phy_ > > functions instead of raw mdiobus writes > > mhh after reading, > https://lore.kernel.org/netdev/CA+h21hoq2qkmxDFEb2QgLfrbC0PYRBHsca=0cDcGOr3txy9hsg@mail.gmail.com/ > this seems to be the wrong way of doing it. > > -michael FWIW, some time after the merge window closes, I plan to convert the felix and seville drivers to mdio_device. It wouldn't be such a big deal to also convert enetc to phylink then, and also do this phy_device -> mdio_device for it too. Thanks, -Vladimir
Am 2020-05-28 10:43, schrieb Vladimir Oltean: > On Thu, 28 May 2020 at 11:18, Michael Walle <michael@walle.cc> wrote: >> >> Am 2020-05-28 08:38, schrieb Michael Walle: >> > These patches were picked from the following series: >> > https://lore.kernel.org/netdev/1567779344-30965-1-git-send-email-claudiu.manoil@nxp.com/ >> > They have never been resent. I've picked them up, addressed Andrews >> > comments, fixed some more bugs and asked Claudiu if I can keep their >> > SOB >> > tags; he agreed. I've tested this on our board which happens to have a >> > bootloader which doesn't do the enetc setup in all cases. Though, only >> > SGMII mode was tested. >> > >> > changes since v2: >> > - removed SOBs from "net: enetc: Initialize SerDes for SGMII and >> > USXGMII >> > protocols" because almost everything has changed. >> > - get a phy_device for the internal PCS PHY so we can use the phy_ >> > functions instead of raw mdiobus writes >> >> mhh after reading, >> https://lore.kernel.org/netdev/CA+h21hoq2qkmxDFEb2QgLfrbC0PYRBHsca=0cDcGOr3txy9hsg@mail.gmail.com/ >> this seems to be the wrong way of doing it. >> >> -michael > > FWIW, some time after the merge window closes, I plan to convert the > felix and seville drivers to mdio_device. It wouldn't be such a big > deal to also convert enetc to phylink then, and also do this > phy_device -> mdio_device for it too. Btw. you/we can also remove that magic SGMII link timer numbers: #define ENETC_PCS_LINK_TIMER_VAL(ms) \ ((u32)(125000000 * (ms) / 1000)) Then for SGMII its ENETC_PCS_LINK_TIMER_VAL(1.6) and for 1000BaseX (and 2500BaseX?) its ENETC_PCS_LINK_TIMER_VAL(10) (which also match to the default value in the registers). Please note, that the current hardcoded values doesn't match the calculated ones precisely. I don't know where these are coming from, but the 1.6ms matches the SGMII spec. -michael