From patchwork Tue Oct 29 17:48:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1186237 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="tX4838po"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 472fS22Ltfz9sPl for ; Wed, 30 Oct 2019 04:57:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726713AbfJ2R5H (ORCPT ); Tue, 29 Oct 2019 13:57:07 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:43361 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726979AbfJ2R5G (ORCPT ); Tue, 29 Oct 2019 13:57:06 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 77DE622E07; Tue, 29 Oct 2019 18:48:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572371332; bh=RCNspeC1Ti2bR8xaR18uPqh3L4hI0ngXx7w3MFF8udI=; h=From:To:Cc:Subject:Date:From; b=tX4838poUDH8IDslIqg8j1gOEwLUI3122XfqbRIer1pvk+V3pgABHPskWha53Thl6 N/kPKE22LlJdqHvBEDjCqC5hFYyRL/QZacQDVEWBq/BGLuNlVsjslCK9inA59Bkn17 E7eFwQE2cCh0VVGWrn3ETVe09bNuaosvWVnXEH6Y= From: Michael Walle To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Michael Walle , Andrew Lunn , Florian Fainelli , Heiner Kallweit , "David S. Miller" , Rob Herring , Mark Rutland Subject: [PATCH 0/3] net: phy: initialize PHYs via device tree properties Date: Tue, 29 Oct 2019 18:48:16 +0100 Message-Id: <20191029174819.3502-1-michael@walle.cc> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org I was trying to configure the Atheros PHY for my board. There are fixups all over the place, for example to enable the 125MHz clock output in almost any i.MX architecture. Instead of adding another fixup in architecture specific code, try to provide a generic way to init the PHY registers. This patch series tries to pick up the "broadcom,reg-init" and "marvell,reg-init" device tree properties idea and make it a more generic "reg-init" which is handled by phy_device instead of a particular phy driver. Michael Walle (3): dt-bindings: net: phy: Add reg-init property net: phy: export __phy_{read|write}_page net: phy: Use device tree properties to initialize any PHYs .../devicetree/bindings/net/ethernet-phy.yaml | 31 ++++++ MAINTAINERS | 1 + drivers/net/phy/phy-core.c | 24 ++++- drivers/net/phy/phy_device.c | 97 ++++++++++++++++++- include/dt-bindings/net/phy.h | 18 ++++ include/linux/phy.h | 2 + 6 files changed, 170 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/net/phy.h Cc: Andrew Lunn Cc: Florian Fainelli Cc: Heiner Kallweit Cc: "David S. Miller" Cc: Rob Herring Cc: Mark Rutland