| Message ID | 20190808123026.17382-1-alexandru.ardelean@analog.com |
|---|---|
| Headers | show |
| Series | net: phy: adin: add support for Analog Devices PHYs | expand |
From: Alexandru Ardelean <alexandru.ardelean@analog.com> Date: Thu, 8 Aug 2019 15:30:11 +0300 > This changeset adds support for Analog Devices Industrial Ethernet PHYs. > Particularly the PHYs this driver adds support for: > * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY > * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit > Ethernet PHY > > The 2 chips are pin & register compatible with one another. The main > difference being that ADIN1200 doesn't operate in gigabit mode. > > The chips can be operated by the Generic PHY driver as well via the > standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the > kernel as well. This assumes that configuration of the PHY has been done > completely in HW, according to spec, i.e. no extra SW configuration > required. > > This changeset also implements the ability to configure the chips via SW > registers. > > Datasheets: > https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf > https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf > > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> I think, at a minimum, the c22 vs. c45 issues need to be discussed more and even if no code changes occur there is definitely some adjustments and clairifications that need to occur on this issue in the commit messages and/or documentation.
On Thu, 2019-08-08 at 11:24 -0700, David Miller wrote: > [External] > > From: Alexandru Ardelean <alexandru.ardelean@analog.com> > Date: Thu, 8 Aug 2019 15:30:11 +0300 > > > This changeset adds support for Analog Devices Industrial Ethernet PHYs. > > Particularly the PHYs this driver adds support for: > > * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY > > * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit > > Ethernet PHY > > > > The 2 chips are pin & register compatible with one another. The main > > difference being that ADIN1200 doesn't operate in gigabit mode. > > > > The chips can be operated by the Generic PHY driver as well via the > > standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the > > kernel as well. This assumes that configuration of the PHY has been done > > completely in HW, according to spec, i.e. no extra SW configuration > > required. > > > > This changeset also implements the ability to configure the chips via SW > > registers. > > > > Datasheets: > > https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf > > https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf > > > > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> > > I think, at a minimum, the c22 vs. c45 issues need to be discussed more > and even if no code changes occur there is definitely some adjustments > and clairifications that need to occur on this issue in the commit > messages and/or documentation. I guess I'll drop/defer some of the C45 stuff for now. I don't know how decisions were done when the chips were created. I am told that C45 works, but I may need to find out more on my end, since I am also new to/unclear on some items. [My personal feeling about this] I think there are some confusions [internally on our side] about what C45 is and how it should be done. I guess it's part of developing knowledge/skills for developing PHYs as a company. There's plenty of knowledge for how to do the electrical, low-power-stuff, etc, and even the datasheet sometimes feels like it's for an ADC/DAC. [My personal feeling about this] Thanks Alex
This changeset adds support for Analog Devices Industrial Ethernet PHYs. Particularly the PHYs this driver adds support for: * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit Ethernet PHY The 2 chips are pin & register compatible with one another. The main difference being that ADIN1200 doesn't operate in gigabit mode. The chips can be operated by the Generic PHY driver as well via the standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the kernel as well. This assumes that configuration of the PHY has been done completely in HW, according to spec, i.e. no extra SW configuration required. This changeset also implements the ability to configure the chips via SW registers. Datasheets: https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Alexandru Ardelean (15): net: phy: adin: add support for Analog Devices PHYs net: phy: adin: hook genphy_read_abilities() to get_features net: phy: adin: hook genphy_{suspend,resume} into the driver net: phy: adin: add support for interrupts net: phy: adin: add {write,read}_mmd hooks net: phy: adin: configure RGMII/RMII/MII modes on config net: phy: adin: make RGMII internal delays configurable net: phy: adin: make RMII fifo depth configurable net: phy: adin: add support MDI/MDIX/Auto-MDI selection net: phy: adin: add EEE translation layer from Clause 45 to Clause 22 net: phy: adin: implement PHY subsystem software reset net: phy: adin: implement Energy Detect Powerdown mode net: phy: adin: configure downshift on config_init net: phy: adin: add ethtool get_stats support dt-bindings: net: add bindings for ADIN PHY driver .../devicetree/bindings/net/adi,adin.yaml | 76 ++ MAINTAINERS | 8 + drivers/net/phy/Kconfig | 9 + drivers/net/phy/Makefile | 1 + drivers/net/phy/adin.c | 732 ++++++++++++++++++ 5 files changed, 826 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/adi,adin.yaml create mode 100644 drivers/net/phy/adin.c