mbox series

[v1,net-next,0/4] Add EHL and TGL PCI info and PCI ID

Message ID 1566869891-29239-1-git-send-email-weifeng.voon@intel.com
Headers show
Series Add EHL and TGL PCI info and PCI ID | expand

Message

Voon, Weifeng Aug. 27, 2019, 1:38 a.m. UTC 
In order to keep PCI info simple and neat, this patch series have
introduced a 3 hierarchy of struct. First layer will be the
intel_mgbe_common_data struct which keeps all Intel common configuration.
Second layer will be xxx_common_data which keeps all the different Intel
microarchitecture, e.g tgl, ehl. The third layer will be configuration
that tied to the PCI ID only based on speed and RGMII/SGMII interface.

EHL and TGL will also having a higher system clock which is 200Mhz.

Voon Weifeng (4):
  net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID
  net: stmmac: add TGL SGMII 1Gbps PCI info and PCI ID
  net: stmmac: add EHL RGMII 1Gbps PCI info and PCI ID
  net: stmmac: setup higher frequency clk support for EHL & TGL

 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 172 +++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c |   3 +
 include/linux/stmmac.h                           |   1 +
 3 files changed, 176 insertions(+)

Comments

David Miller Aug. 28, 2019, 4:59 a.m. UTC | #1 
From: Voon Weifeng <weifeng.voon@intel.com>
Date: Tue, 27 Aug 2019 09:38:07 +0800

> In order to keep PCI info simple and neat, this patch series have
> introduced a 3 hierarchy of struct. First layer will be the
> intel_mgbe_common_data struct which keeps all Intel common configuration.
> Second layer will be xxx_common_data which keeps all the different Intel
> microarchitecture, e.g tgl, ehl. The third layer will be configuration
> that tied to the PCI ID only based on speed and RGMII/SGMII interface.
> 
> EHL and TGL will also having a higher system clock which is 200Mhz.

Series applied.