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[net-next,v3,00/19] Xilinx axienet driver updates (v3)

Message ID 1559684626-24775-1-git-send-email-hancock@sedsystems.ca
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Series Xilinx axienet driver updates (v3) | expand

Message

Robert Hancock June 4, 2019, 9:43 p.m. UTC
This is a series of enhancements and bug fixes in order to get the mainline
version of this driver into a more generally usable state, including on
x86 or ARM platforms. It also converts the driver to use the phylink API
in order to provide support for SFP modules.

Changes since v2:
-Fixed MDIO bus parent detection as suggested by Andrew Lunn
-Use clock framework to detect AXI bus clock rather than having to explicitly
 specify MDIO clock divisor
-Hold MDIO bus lock around device resets to avoid concurrent MDIO accesses
-Fix bug in "Make missing MAC address non-fatal" patch

Robert Hancock (19):
  net: axienet: Fix casting of pointers to u32
  net: axienet: Use standard IO accessors
  net: axienet: fix MDIO bus naming
  net: axienet: add X86 and ARM as supported platforms
  net: axienet: Use clock framework to get device clock rate
  net: axienet: fix teardown order of MDIO bus
  net: axienet: Re-initialize MDIO registers properly after reset
  net: axienet: Cleanup DMA device reset and halt process
  net: axienet: Make RX/TX ring sizes configurable
  net: axienet: Add DMA registers to ethtool register dump
  net: axienet: Support shared interrupts
  net: axienet: Add optional support for Ethernet core interrupt
  net: axienet: Fix race condition causing TX hang
  net: axienet: Make missing MAC address non-fatal
  net: axienet: stop interface during shutdown
  net: axienet: Fix MDIO bus parent node detection
  net: axienet: document axistream-connected attribute
  net: axienet: make use of axistream-connected attribute optional
  net: axienet: convert to phylink API

 .../devicetree/bindings/net/xilinx_axienet.txt     |  26 +-
 drivers/net/ethernet/xilinx/Kconfig                |   6 +-
 drivers/net/ethernet/xilinx/xilinx_axienet.h       |  35 +-
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c  | 677 ++++++++++++++-------
 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c  | 112 ++--
 5 files changed, 593 insertions(+), 263 deletions(-)

Comments

Andrew Lunn June 4, 2019, 9:58 p.m. UTC | #1
On Tue, Jun 04, 2019 at 03:43:27PM -0600, Robert Hancock wrote:
> This is a series of enhancements and bug fixes in order to get the mainline
> version of this driver into a more generally usable state, including on
> x86 or ARM platforms. It also converts the driver to use the phylink API
> in order to provide support for SFP modules.
> 
> Changes since v2:
> -Fixed MDIO bus parent detection as suggested by Andrew Lunn
> -Use clock framework to detect AXI bus clock rather than having to explicitly
>  specify MDIO clock divisor
> -Hold MDIO bus lock around device resets to avoid concurrent MDIO accesses
> -Fix bug in "Make missing MAC address non-fatal" patch

Hi Robert

When you repost, please include all reviewed-by, acked-by tags etc.

     Andrew