| Message ID | 1556126241-2774-1-git-send-email-weifeng.voon@intel.com |
|---|---|
| Headers | show |
| Series | net: stmmac: enable EHL SGMII | expand |
From: Weifeng Voon <weifeng.voon@intel.com> Date: Wed, Apr 24, 2019 at 18:17:14 > From: "Voon, Weifeng" <weifeng.voon@intel.com@intel.com> > > This patch-set is to enable Ethernet controller (DW Ethernet QoS > and DW Ethernet PCS) with SGMII interface in Elkhart Lake. The > DW Ethernet PCS is the Physical Coding Sublayer that is between > Ethernet MAC and PHY and uses MDIO Clause-45 as Communication. > Please re-send this series with the stmmac maintainers in CC. Also CC Andrew Lunn and Florian Fainelli for the C45 part. Thanks, Jose Miguel Abreu
On Thu, Apr 25, 2019 at 01:17:14AM +0800, Weifeng Voon wrote: > From: "Voon, Weifeng" <weifeng.voon@intel.com@intel.com> > > This patch-set is to enable Ethernet controller (DW Ethernet QoS > and DW Ethernet PCS) with SGMII interface in Elkhart Lake. Can the hardware also do 1000BaseX? Andrew
> From: "Voon, Weifeng" <weifeng.voon@intel.com@intel.com> > > This patch-set is to enable Ethernet controller (DW Ethernet QoS and DW > Ethernet PCS) with SGMII interface in Elkhart Lake. The DW Ethernet PCS is > the Physical Coding Sublayer that is between Ethernet MAC and PHY and > uses MDIO Clause-45 as Communication. > > Kweh Hock Leong (1): > net: stmmac: enable clause 45 mdio support > > Ong Boon Leong (3): > net: stmmac: introducing support for DWC xPCS logics > net: stmmac: add xpcs function hooks into main driver and ethtool > net: stmmac: add xPCS functions for device with DWMACv5.1 > > Weifeng Voon (3): > net: stmmac: add EHL SGMII 1Gbps platform data and PCI ID > net: stmmac: dma channel control register need to be init first > net: stmmac: add xPCS platform data for EHL > > drivers/net/ethernet/stmicro/stmmac/dw_xpcs.h | 288 > +++++++++++++++++++++ > drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 67 +++++ > drivers/net/ethernet/stmicro/stmmac/hwif.c | 31 ++- > drivers/net/ethernet/stmicro/stmmac/hwif.h | 18 ++ > drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 + > .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 14 + > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 58 ++++- > drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 36 ++- > drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 108 ++++++++ > include/linux/phy.h | 2 + > include/linux/stmmac.h | 3 + > 11 files changed, 616 insertions(+), 11 deletions(-) create mode 100644 > drivers/net/ethernet/stmicro/stmmac/dw_xpcs.h > > -- > 1.9.1 ++ stmmac maintainers and c45 experts
> > This patch-set is to enable Ethernet controller (DW Ethernet QoS and > > DW Ethernet PCS) with SGMII interface in Elkhart Lake. > > Can the hardware also do 1000BaseX? Yes, it is able to do 1000BaseX. Regards, Weifeng > > Andrew
On Thu, Apr 25, 2019 at 07:27:51AM +0000, Voon, Weifeng wrote: > > > This patch-set is to enable Ethernet controller (DW Ethernet QoS and > > > DW Ethernet PCS) with SGMII interface in Elkhart Lake. > > > > Can the hardware also do 1000BaseX? > > Yes, it is able to do 1000BaseX. I Voon That means you should not really hard code it to SGMII. Somebody is going to connect an SFP or an Ethernet switch and want to use 1000BaseX. At minimum, please add support for phy-mode in the device tree. Also, when the adjust_link callback passed to phy_connect() is called, you can look at the interface type to know if you need to configure it to SGMII or 1000BaseX. A copper PHY in an SFP module generally wants SGMII, but an optical module wants 1000BaseX. But to properly support SPFs the driver needs to swap to phylink, rather than phylib. Andrew
>-----Original Message----- >From: Andrew Lunn [mailto:andrew@lunn.ch] >Sent: Thursday, April 25, 2019 8:38 PM >To: Voon, Weifeng <weifeng.voon@intel.com> >Cc: David S. Miller <davem@davemloft.net>; netdev@vger.kernel.org; linux- >kernel@vger.kernel.org; Ong, Boon Leong <boon.leong.ong@intel.com>; >Kweh, Hock Leong <hock.leong.kweh@intel.com>; Florian Fainelli ><f.fainelli@gmail.com>; Maxime Coquelin <mcoquelin.stm32@gmail.com>; >Giuseppe Cavallaro <peppe.cavallaro@st.com>; Jose Abreu ><joabreu@synopsys.com> >Subject: Re: [PATCH 0/7] net: stmmac: enable EHL SGMII > >On Thu, Apr 25, 2019 at 07:27:51AM +0000, Voon, Weifeng wrote: >> > > This patch-set is to enable Ethernet controller (DW Ethernet QoS and >> > > DW Ethernet PCS) with SGMII interface in Elkhart Lake. >> > >> > Can the hardware also do 1000BaseX? >> >> Yes, it is able to do 1000BaseX. > >I Voon > >That means you should not really hard code it to SGMII. Somebody is >going to connect an SFP or an Ethernet switch and want to use >1000BaseX. Hi Andrew, The Ethernet controller consists of two ways to connect to external PHY, RGMII and SGMII. The selection is done through soft strap. The patch-series is to enable SGMII interface. The DW xPCS IP is configured to operate in 1000BASE-X mode. The xPCS IP is external connected through internal PHY interface which presents externally as SGMII interface. To help illustrate the connection:- <-----------------GBE Controller----------------->|<--External PHY chip--> +----------+ +----+ +---+ +-----------------+ | EQoS | <-GMII->|xPCS|<--> | L1 | <-- SGMII --> | External GbE | | MAC | | | |PHY| | PHY Chip | +----------+ +----+ +---+ +-----------------+ In future, we will submit the changes for the RGMII connection that bypasses DW xPCS. Hope this help clarifies matter. >At minimum, please add support for phy-mode in the device tree. > >Also, when the adjust_link callback passed to phy_connect() is called, >you can look at the interface type to know if you need to configure it >to SGMII or 1000BaseX. A copper PHY in an SFP module generally wants >SGMII, but an optical module wants 1000BaseX. But to properly support >SPFs the driver needs to swap to phylink, rather than phylib. > > Andrew
> >> > > This patch-set is to enable Ethernet controller (DW Ethernet QoS and > >> > > DW Ethernet PCS) with SGMII interface in Elkhart Lake. > >> > > >> > Can the hardware also do 1000BaseX? > >> > >> Yes, it is able to do 1000BaseX. > > > >I Voon > > > >That means you should not really hard code it to SGMII. Somebody is > >going to connect an SFP or an Ethernet switch and want to use > >1000BaseX. > > Hi Andrew, > > The Ethernet controller consists of two ways to connect to external PHY, > RGMII and SGMII. The selection is done through soft strap. > The patch-series is to enable SGMII interface. The DW xPCS IP is > configured to operate in 1000BASE-X mode. The xPCS IP is external > connected through internal PHY interface which presents externally > as SGMII interface. To help illustrate the connection:- > > <-----------------GBE Controller----------------->|<--External PHY chip--> > > +----------+ +----+ +---+ +-----------------+ > | EQoS | <-GMII->|xPCS|<--> | L1 | <-- SGMII --> | External GbE | > | MAC | | | |PHY| | PHY Chip | > +----------+ +----+ +---+ +-----------------+ > > In future, we will submit the changes for the RGMII connection that > bypasses DW xPCS. The ASCII art get messed up somewhere. What you are implementing looks like: <-----------------GBE Controller------------>|<--External PHY chip--> +----------+ +----+ +---+ | EQoS | <-GMII->|xPCS|<--> | L1 | <-- SGMII --> |PHY| | MAC | | | +---+ +----------+ +----+ With the Ethernet controller, the MAC connects to the xPCS. Out of the xPCS you have a SERDES connection, running the SGMII protocol. That connects to external pins of the SoC. These are then connected to a copper PHY which also supports SGMII. What i'm trying to understand is if the following is possible: <-----------------GBE Controller------------->|<--External SFP cage/module--> +----------+ +----+ +---+ | EQoS | <-GMII->|xPCS|<--> | L1 | <-- 1000BaseX --> |SPF| | MAC | | | +---+ +----------+ +----+ Rather than use a Copper PHY, an SFP cage+module is used. The same SERDES interface is used, but 1000BaseX runs over it. Generally, an xPCS which can run SGMII can also do 1000BaseX, because SGMII is just some Cisco Proprietary extensions to 1000BaseX. If the xPCS can do 1000BaseX over the SERDES, you should not hard code it to SGMII, but allow it to be configured. Andrew
>-----Original Message----- >From: Andrew Lunn [mailto:andrew@lunn.ch] >Sent: Thursday, April 25, 2019 11:24 PM >To: Ong, Boon Leong <boon.leong.ong@intel.com> >Cc: Voon, Weifeng <weifeng.voon@intel.com>; David S. Miller ><davem@davemloft.net>; netdev@vger.kernel.org; linux- >kernel@vger.kernel.org; Kweh, Hock Leong <hock.leong.kweh@intel.com>; >Florian Fainelli <f.fainelli@gmail.com>; Maxime Coquelin ><mcoquelin.stm32@gmail.com>; Giuseppe Cavallaro ><peppe.cavallaro@st.com>; Jose Abreu <joabreu@synopsys.com> >Subject: Re: [PATCH 0/7] net: stmmac: enable EHL SGMII > >> >> > > This patch-set is to enable Ethernet controller (DW Ethernet QoS and >> >> > > DW Ethernet PCS) with SGMII interface in Elkhart Lake. >> >> > >> >> > Can the hardware also do 1000BaseX? >> >> >> >> Yes, it is able to do 1000BaseX. >> > >> >I Voon >> > >> >That means you should not really hard code it to SGMII. Somebody is >> >going to connect an SFP or an Ethernet switch and want to use >> >1000BaseX. >> >> Hi Andrew, >> >> The Ethernet controller consists of two ways to connect to external PHY, >> RGMII and SGMII. The selection is done through soft strap. >> The patch-series is to enable SGMII interface. The DW xPCS IP is >> configured to operate in 1000BASE-X mode. The xPCS IP is external >> connected through internal PHY interface which presents externally >> as SGMII interface. To help illustrate the connection:- >> >> <-----------------GBE Controller----------------->|<--External PHY chip--> >> >> +----------+ +----+ +---+ +-----------------+ >> | EQoS | <-GMII->|xPCS|<--> | L1 | <-- SGMII --> | External GbE | >> | MAC | | | |PHY| | PHY Chip | >> +----------+ +----+ +---+ +-----------------+ >> >> In future, we will submit the changes for the RGMII connection that >> bypasses DW xPCS. > >The ASCII art get messed up somewhere. Sorry for that. > >What you are implementing looks like: > > > <-----------------GBE Controller------------>|<--External PHY chip--> > > +----------+ +----+ +---+ > | EQoS | <-GMII->|xPCS|<--> | L1 | <-- SGMII --> |PHY| > | MAC | | | +---+ > +----------+ +----+ > >With the Ethernet controller, the MAC connects to the xPCS. Out of the >xPCS you have a SERDES connection, running the SGMII protocol. That >connects to external pins of the SoC. These are then connected to a >copper PHY which also supports SGMII. > >What i'm trying to understand is if the following is possible: > > <-----------------GBE Controller------------->|<--External SFP cage/module--> > > +----------+ +----+ +---+ > | EQoS | <-GMII->|xPCS|<--> | L1 | <-- 1000BaseX --> |SPF| > | MAC | | | +---+ > +----------+ +----+ > >Rather than use a Copper PHY, an SFP cage+module is used. The same >SERDES interface is used, but 1000BaseX runs over it. > >Generally, an xPCS which can run SGMII can also do 1000BaseX, because >SGMII is just some Cisco Proprietary extensions to 1000BaseX. > >If the xPCS can do 1000BaseX over the SERDES, you should not hard code >it to SGMII, but allow it to be configured. Thanks for the review and checking above. Sorry for the delay, we have checked with hardware/SoC HW architect and gotten confirmation that the controller can only support SGMII inter-chip connection. It does not support 1000Base-X. In this case, we believe that the current implementation of the DW xPCS are sufficient. Ok?
> Sorry for the delay, we have checked with hardware/SoC HW architect > and gotten confirmation that the controller can only support SGMII inter-chip > connection. It does not support 1000Base-X. O.K, i'm surprised about that, but if that is what the hardware engineer says... > In this case, we believe that the current implementation of the DW xPCS > are sufficient. Ok? Yes, if all i can do is SGMII, hard coding SGMII is fine. But you should probably check phy-mode and return an error if it has a value other than SGMII, Andrew
From: Andrew Lunn <andrew@lunn.ch> Date: Mon, Apr 29, 2019 at 14:10:16 > Yes, if all i can do is SGMII, hard coding SGMII is fine. But you > should probably check phy-mode and return an error if it has a value > other than SGMII, +1 because XPCS supports 1000Base-X but it seems this SoC doesn't. Thanks, Jose Miguel Abreu
From: "Voon, Weifeng" <weifeng.voon@intel.com@intel.com> This patch-set is to enable Ethernet controller (DW Ethernet QoS and DW Ethernet PCS) with SGMII interface in Elkhart Lake. The DW Ethernet PCS is the Physical Coding Sublayer that is between Ethernet MAC and PHY and uses MDIO Clause-45 as Communication. Kweh Hock Leong (1): net: stmmac: enable clause 45 mdio support Ong Boon Leong (3): net: stmmac: introducing support for DWC xPCS logics net: stmmac: add xpcs function hooks into main driver and ethtool net: stmmac: add xPCS functions for device with DWMACv5.1 Weifeng Voon (3): net: stmmac: add EHL SGMII 1Gbps platform data and PCI ID net: stmmac: dma channel control register need to be init first net: stmmac: add xPCS platform data for EHL drivers/net/ethernet/stmicro/stmmac/dw_xpcs.h | 288 +++++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 67 +++++ drivers/net/ethernet/stmicro/stmmac/hwif.c | 31 ++- drivers/net/ethernet/stmicro/stmmac/hwif.h | 18 ++ drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 + .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 14 + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 58 ++++- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 36 ++- drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 108 ++++++++ include/linux/phy.h | 2 + include/linux/stmmac.h | 3 + 11 files changed, 616 insertions(+), 11 deletions(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw_xpcs.h -- 1.9.1