Message ID | 4a6eea8cfd1cd28fccfae067026bff30cbec1d4b.1729271995.git.ritesh.list@gmail.com (mailing list archive) |
---|---|
State | Under Review |
Headers | show
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Fri, 18 Oct 2024 10:31:16 -0700 (PDT) From: "Ritesh Harjani (IBM)" <ritesh.list@gmail.com> To: linuxppc-dev@lists.ozlabs.org Cc: kasan-dev@googlegroups.com, linux-mm@kvack.org, Marco Elver <elver@google.com>, Alexander Potapenko <glider@google.com>, Heiko Carstens <hca@linux.ibm.com>, Michael Ellerman <mpe@ellerman.id.au>, Nicholas Piggin <npiggin@gmail.com>, Madhavan Srinivasan <maddy@linux.ibm.com>, Christophe Leroy <christophe.leroy@csgroup.eu>, Hari Bathini <hbathini@linux.ibm.com>, "Aneesh Kumar K . V" <aneesh.kumar@kernel.org>, Donet Tom <donettom@linux.vnet.ibm.com>, Pavithra Prakash <pavrampu@linux.vnet.ibm.com>, LKML <linux-kernel@vger.kernel.org>, "Ritesh Harjani (IBM)" <ritesh.list@gmail.com> Subject: [PATCH v3 11/12] book3s64/hash: Disable kfence if not early init Date: Fri, 18 Oct 2024 22:59:52 +0530 Message-ID: <4a6eea8cfd1cd28fccfae067026bff30cbec1d4b.1729271995.git.ritesh.list@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <cover.1729271995.git.ritesh.list@gmail.com> References: <cover.1729271995.git.ritesh.list@gmail.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: <linuxppc-dev.lists.ozlabs.org> List-Help: <mailto:linuxppc-dev+help@lists.ozlabs.org> List-Post: <mailto:linuxppc-dev@lists.ozlabs.org> List-Subscribe: <mailto:linuxppc-dev+subscribe@lists.ozlabs.org>, <mailto:linuxppc-dev+subscribe-digest@lists.ozlabs.org>, <mailto:linuxppc-dev+subscribe-nomail@lists.ozlabs.org> List-Unsubscribe: <mailto:linuxppc-dev+unsubscribe@lists.ozlabs.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=disabled version=4.0.0 X-Spam-Checker-Version: SpamAssassin 4.0.0 (2022-12-13) on lists.ozlabs.org |
Series |
powerpc/kfence: Improve kfence support (mainly Hash)
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expand
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diff --git a/arch/powerpc/mm/book3s64/hash_utils.c b/arch/powerpc/mm/book3s64/hash_utils.c index 558d6f5202b9..2f5dd6310a8f 100644 --- a/arch/powerpc/mm/book3s64/hash_utils.c +++ b/arch/powerpc/mm/book3s64/hash_utils.c @@ -410,6 +410,8 @@ static phys_addr_t kfence_pool; static inline void hash_kfence_alloc_pool(void) { + if (!kfence_early_init_enabled()) + goto err; /* allocate linear map for kfence within RMA region */ linear_map_kf_hash_count = KFENCE_POOL_SIZE >> PAGE_SHIFT; @@ -1074,7 +1076,7 @@ static void __init htab_init_page_sizes(void) bool aligned = true; init_hpte_page_sizes(); - if (!debug_pagealloc_enabled_or_kfence()) { + if (!debug_pagealloc_enabled() && !kfence_early_init_enabled()) { /* * Pick a size for the linear mapping. Currently, we only * support 16M, 1M and 4K which is the default
Enable kfence on book3s64 hash only when early init is enabled. This is because, kfence could cause the kernel linear map to be mapped at PAGE_SIZE level instead of 16M (which I guess we don't want). Also currently there is no way to - 1. Make multiple page size entries for the SLB used for kernel linear map. 2. No easy way of getting the hash slot details after the page table mapping for kernel linear setup. So even if kfence allocate the pool in late init, we won't be able to get the hash slot details in kfence linear map. Thus this patch disables kfence on hash if kfence early init is not enabled. Signed-off-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com> --- arch/powerpc/mm/book3s64/hash_utils.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)