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Tue, 3 Sep 2024 13:15:02 -0400 (EDT) From: Jiaxun Yang Date: Tue, 03 Sep 2024 18:14:36 +0100 Subject: [PATCH 3/3] rust: Enable for MIPS MIME-Version: 1.0 Message-Id: <20240903-mips-rust-v1-3-0fdf0b2fd58f@flygoat.com> References: <20240903-mips-rust-v1-0-0fdf0b2fd58f@flygoat.com> In-Reply-To: <20240903-mips-rust-v1-0-0fdf0b2fd58f@flygoat.com> To: Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Thomas Bogendoerfer , Steven Rostedt , Masami Hiramatsu , Mark Rutland , Jonathan Corbet , Alex Shi , Yanteng Si , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, linux-mips@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5640; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=dTzaFLygGDWP88YqbuvgFJnSRc3/FfsgZOCccEPIFZI=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTrLmy/VbhlTd99/7KW13KPufKGBw0FkU1B7Dszj5oUa Qn6Pl/ZUcrCIMbFICumyBIioNS3ofHigusPsv7AzGFlAhnCwMUpABPZNZeR4eFshrNzVwhttrhd 0yf5Z2d9yQ2X7gU8oWbsP76u15z0Q42RoefwMqE02eP7ns+pn328K6qhZqVvJm/ItXsCWye+OCD HzwwA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240903_101507_397190_CD76F114 X-CRM114-Status: GOOD ( 13.06 ) X-Spam-Score: -2.8 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Enable rust for linux by implement generate_rust_target.rs and select relevant Kconfig options. We don't use builtin target as there is no sutiable baremetal target for us that can cover all ISA variants supported by kernel. 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X-BeenThere: linux-um@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-um" Errors-To: linux-um-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Enable rust for linux by implement generate_rust_target.rs and select relevant Kconfig options. We don't use builtin target as there is no sutiable baremetal target for us that can cover all ISA variants supported by kernel. Link: https://github.com/Rust-for-Linux/linux/issues/107 Signed-off-by: Jiaxun Yang --- Documentation/rust/arch-support.rst | 1 + .../translations/zh_CN/rust/arch-support.rst | 1 + arch/mips/Kconfig | 2 + scripts/generate_rust_target.rs | 64 ++++++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst index 750ff371570a..ab6c0ae5a407 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -17,6 +17,7 @@ Architecture Level of support Constraints ============= ================ ============================================== ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- +``mips`` Maintained \- ``riscv`` Maintained ``riscv64`` only. ``um`` Maintained \- ``x86`` Maintained ``x86_64`` only. diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst index abd708d48f82..1eaa6c3297ac 100644 --- a/Documentation/translations/zh_CN/rust/arch-support.rst +++ b/Documentation/translations/zh_CN/rust/arch-support.rst @@ -21,6 +21,7 @@ ============= ================ ============================================== ``arm64`` Maintained 只有小端序 ``loongarch`` Maintained \- +``mips`` Maintained \- ``riscv`` Maintained 只有 ``riscv64`` ``um`` Maintained 只有 ``x86_64`` ``x86`` Maintained 只有 ``x86_64`` diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 43da6d596e2b..a91f0a4fd8e9 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -90,6 +90,8 @@ config MIPS select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ + select HAVE_RUST + select HAVE_GENERATE_RUST_TARGET select HAVE_SPARSE_SYSCALL_NR select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs index 863720777313..2b8054f17c47 100644 --- a/scripts/generate_rust_target.rs +++ b/scripts/generate_rust_target.rs @@ -141,6 +141,13 @@ fn has(&self, option: &str) -> bool { let option = "CONFIG_".to_owned() + option; self.0.contains_key(&option) } + + /// Returns the value of the option in the configuration. + /// The argument must be passed without the `CONFIG_` prefix. + fn get(&self, option: &str) -> Option<&String> { + let option = "CONFIG_".to_owned() + option; + self.0.get(&option) + } } fn main() { @@ -203,6 +210,63 @@ fn main() { ts.push("target-pointer-width", "32"); } else if cfg.has("LOONGARCH") { panic!("loongarch uses the builtin rustc loongarch64-unknown-none-softfloat target"); + } else if cfg.has("MIPS") { + let mut features = "+soft-float,+noabicalls".to_string(); + + if cfg.has("64BIT") { + ts.push("arch", "mips64"); + ts.push("abi", "abi64"); + cfg.get("TARGET_ISA_REV").map(|isa_rev| { + let feature = match isa_rev.as_str() { + "1" => ",+mips64", + "2" => ",+mips64r2", + "5" => ",+mips64r5", + "6" => ",+mips64r6", + _ => ",+mips3", + }; + features += feature; + }); + + ts.push("features", features); + if cfg.has("CPU_BIG_ENDIAN") { + ts.push( + "data-layout", + "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", + ); + ts.push("llvm-target", "mips64-unknown-linux-gnuabi64"); + } else { + ts.push( + "data-layout", + "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", + ); + ts.push("llvm-target", "mips64el-unknown-linux-gnuabi64"); + } + ts.push("target-pointer-width", "64"); + } else { + ts.push("arch", "mips"); + cfg.get("TARGET_ISA_REV").map(|isa_rev| { + let feature = match isa_rev.as_str() { + "1" => ",+mips32", + "2" => ",+mips32r2", + "5" => ",+mips32r5", + "6" => ",+mips32r6", + _ => ",+mips2", + }; + features += feature; + }); + + ts.push("features", features); + if cfg.has("CPU_BIG_ENDIAN") { + ts.push("data-layout", + "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); + ts.push("llvm-target", "mips-unknown-linux-gnu"); + } else { + ts.push("data-layout", + "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); + ts.push("llvm-target", "mipsel-unknown-linux-gnu"); + } + ts.push("target-pointer-width", "32"); + } } else { panic!("Unsupported architecture"); }