Message ID | 20240701151231.29425-13-kyarlagadda@nvidia.com |
---|---|
State | Rejected |
Headers | show
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Mon, 1 Jul 2024 08:13:49 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 1 Jul 2024 08:13:49 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 1 Jul 2024 08:13:44 -0700 From: Krishna Yarlagadda <kyarlagadda@nvidia.com> To: <linux-tegra@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-kernel@vger.kernel.org> CC: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <corbet@lwn.net>, <andi.shyti@kernel.org>, <wsa+renesas@sang-engineering.com>, <ulf.hansson@linaro.org>, <adrian.hunter@intel.com>, <digetx@gmail.com>, <ldewangan@nvidia.com>, <kyarlagadda@nvidia.com>, <mkumard@nvidia.com> Subject: [RFC PATCH V2 12/12] arm64: tegra: SDHCI timing settings Date: Mon, 1 Jul 2024 20:42:30 +0530 Message-ID: <20240701151231.29425-13-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240701151231.29425-1-kyarlagadda@nvidia.com> References: <20240701151231.29425-1-kyarlagadda@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: <linux-tegra.vger.kernel.org> List-Subscribe: <mailto:linux-tegra+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-tegra+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|PH0PR12MB8174:EE_ X-MS-Office365-Filtering-Correlation-Id: 36177853-95f8-4dfe-fc22-08dc99e071db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; 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Introduce Tegra register config settings
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expand
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diff --git a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi index 7e5b9c10c617..30c125636123 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi @@ -426,6 +426,34 @@ i2c-standard-cfg { }; + configmmc1: config-mmc3400000 { + + sdhci-mmc-hs200-cfg { + nvidia,num-tuning-iter = <0x2>; + }; + + sdhci-uhs-sdr104-cfg { + nvidia,num-tuning-iter = <0x2>; + }; + + sdhci-uhs-sdr50-cfg { + nvidia,num-tuning-iter = <0x4>; + }; + + }; + + configmmc2: config-mmc3460000 { + + sdhci-mmc-hs200-cfg { + nvidia,num-tuning-iter = <0x2>; + }; + + sdhci-mmc-hs400-cfg { + nvidia,num-tuning-iter = <0x2>; + }; + + }; + }; bus@0 { @@ -461,5 +489,13 @@ i2c@c250000 { config-settings = <&configi2c8>; }; + mmc@3400000 { + config-settings = <&configmmc1>; + }; + + mmc@3460000 { + config-settings = <&configmmc2>; + }; + }; };
Set SDHCI timing registers through config settings for Tegra234 chip and P3701 board. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+)