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bh=YVadnsK4bFte+vfSQ0rGftLRVFRW5Se0kh1kqTWlCPw=; b=plp6XIasK/JZ4NR4CywTAJWb9CohoaqFZF/E4s6N3a8kIOsGtGw9KYc7gK3e3NEPHscrW1 S2yDUAwLuwnCtbZLCB4at99gBkmUWCeZAS+10PZPTq/73eWXN+Rt9Lv68yLOOUVx6rRAxp SOu5zq5QwKI7wiWF4QO7Shjb9qoqR4U= Received: from diogo-gram.BROTERIALX.local (bl10-99-26.dsl.telepac.pt [85.243.99.26]) (Authenticated sender: ist187313) by mail1.tecnico.ulisboa.pt (Postfix) with ESMTPSA id CF6C7360083; Mon, 29 Apr 2024 11:19:47 +0100 (WEST) From: Diogo Ivo To: krzysztof.kozlowski@linaro.org, thierry.reding@gmail.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org Cc: Diogo Ivo Subject: [PATCH v3 2/7] memory: tegra: Move DQSOSC measurement to common place Date: Mon, 29 Apr 2024 11:19:25 +0100 Message-ID: <20240429101933.11500-3-diogo.ivo@tecnico.ulisboa.pt> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240429101933.11500-1-diogo.ivo@tecnico.ulisboa.pt> References: <20240429101933.11500-1-diogo.ivo@tecnico.ulisboa.pt> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move the calls that instruct the RAM to capture its clock tree delays to update_clock_tree_delay() in order to avoid code duplication. Signed-off-by: Diogo Ivo --- Changes in v3: - Rename the delay length variable udelay -> delay_us to fix compile error drivers/memory/tegra/tegra210-emc-cc-r21021.c | 25 ++++++++----------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory/tegra/tegra210-emc-cc-r21021.c index 9ec49ced8f91..a3525f3b8145 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -123,10 +123,19 @@ static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) bool dvfs_update = type == DVFS_UPDATE; s32 tdel = 0, tmdel = 0, adel = 0; bool dvfs_pt1 = type == DVFS_PT1; + u32 temp[2][2], value, delay_us; unsigned long cval = 0; - u32 temp[2][2], value; unsigned int i; + if (dvfs_pt1 || periodic_training_update) { + delay_us = tegra210_emc_actual_osc_clocks(last->run_clocks); + delay_us *= 1000; + delay_us = 2 + (delay_us / last->rate); + + tegra210_emc_start_periodic_compensation(emc); + udelay(delay_us); + } + /* * Dev0 MSB. */ @@ -409,11 +418,6 @@ static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 type, (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) u32 i, adel = 0, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; - u32 delay; - - delay = tegra210_emc_actual_osc_clocks(last->run_clocks); - delay *= 1000; - delay = 2 + (delay / last->rate); if (!next->periodic_training) return 0; @@ -447,9 +451,6 @@ static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 type, __MOVAVG(next, C1D1U1) = 0; for (i = 0; i < samples; i++) { - tegra210_emc_start_periodic_compensation(emc); - udelay(delay); - /* * Generate next sample of data. */ @@ -465,12 +466,8 @@ static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 type, adel = update_clock_tree_delay(emc, DVFS_UPDATE); } - if (type == PERIODIC_TRAINING_SEQUENCE) { - tegra210_emc_start_periodic_compensation(emc); - udelay(delay); - + if (type == PERIODIC_TRAINING_SEQUENCE) adel = update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE); - } return adel; }