| Message ID | 20230208142735.3218707-1-cyndis@kapsi.fi |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [v2] PCI: tegra194: Handle errors in BPMP response | expand |
On Wed, Feb 08, 2023 at 04:27:35PM +0200, Mikko Perttunen wrote: > From: Mikko Perttunen <mperttunen@nvidia.com> > > The return value from tegra_bpmp_transfer indicates the success or > failure of the IPC transaction with BPMP. If the transaction > succeeded, we also need to check the actual command's result code. > Add code to do this. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) Lorenzo asked whether the error check could be incorporated into tegra_bpmp_transfer() in reply to an earlier version of this. It would be possible, but I think it has the downside of loosing some context. The end result would still be the same, but it would make it impossible for the caller to distinguish between a failure of tegra_bpmp_transfer() and a failure of the message transaction. For example the cpufreq driver checks for msg.rx.ret == -BPMP_EINVAL and if that's returned will mark the given cluster as not available. This is special behavior that only makes sense within the context of cpufreq. It wouldn't be possible to make these decisions if tegra_bpmp_transfer() did some automated conversion and effectively rolled the message error into the function return error. So I think this will need to stay as-is to make sure we can handle these errors correctly. Acked-by: Thierry Reding <treding@nvidia.com>
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 02d78a12b6e7..cf5fd1c2efd3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1200,6 +1200,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, struct mrq_uphy_response resp; struct tegra_bpmp_message msg; struct mrq_uphy_request req; + int err; /* * Controller-5 doesn't need to have its state set by BPMP-FW in @@ -1222,7 +1223,13 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, msg.rx.data = &resp; msg.rx.size = sizeof(resp); - return tegra_bpmp_transfer(pcie->bpmp, &msg); + err = tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + return err; + if (msg.rx.ret) + return -EINVAL; + + return 0; } static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, @@ -1231,6 +1238,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, struct mrq_uphy_response resp; struct tegra_bpmp_message msg; struct mrq_uphy_request req; + int err; memset(&req, 0, sizeof(req)); memset(&resp, 0, sizeof(resp)); @@ -1250,7 +1258,13 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, msg.rx.data = &resp; msg.rx.size = sizeof(resp); - return tegra_bpmp_transfer(pcie->bpmp, &msg); + err = tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + return err; + if (msg.rx.ret) + return -EINVAL; + + return 0; } static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)