| Message ID | 20221025182508.10687-1-vidyas@nvidia.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller | expand |
On Tue, Oct 25, 2022 at 11:55:08PM +0530, Vidya Sagar wrote: > Fix the starting address of the non-prefetchable aperture of PCIe C3 > controller. > > Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied, thanks. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5d7df32fd159..85b0dea33117 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2343,7 +2343,7 @@ bus-range = <0x0 0xff>; ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
Fix the starting address of the non-prefetchable aperture of PCIe C3 controller. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)