| Message ID | 20221010100046.6477-1-jonathanh@nvidia.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [V3] clk: tegra: Fix Tegra PWM parent clock | expand |
On Mon, Oct 10, 2022 at 11:00:46AM +0100, Jon Hunter wrote: > Commit 8c193f4714df ("pwm: tegra: Optimize period calculation") updated > the period calculation in the Tegra PWM driver and now returns an error > if the period requested is less than minimum period supported. This is > breaking PWM support on various Tegra platforms. For example, on the > Tegra210 Jetson Nano platform this is breaking the PWM fan support and > probing the PWM fan driver now fails ... > > pwm-fan pwm-fan: Failed to configure PWM: -22 > pwm-fan: probe of pwm-fan failed with error -22 > > The problem is that the default parent clock for the PWM on Tegra210 is > a 32kHz clock and is unable to support the requested PWM period. > > Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by > updating the parent clock for the PWM to be the PLL_P. > > Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20 > Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20 > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30 > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3 Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Thanks for your work on this! Uwe
Quoting Jon Hunter (2022-10-10 03:00:46) > Commit 8c193f4714df ("pwm: tegra: Optimize period calculation") updated > the period calculation in the Tegra PWM driver and now returns an error > if the period requested is less than minimum period supported. This is > breaking PWM support on various Tegra platforms. For example, on the > Tegra210 Jetson Nano platform this is breaking the PWM fan support and > probing the PWM fan driver now fails ... > > pwm-fan pwm-fan: Failed to configure PWM: -22 > pwm-fan: probe of pwm-fan failed with error -22 > > The problem is that the default parent clock for the PWM on Tegra210 is > a 32kHz clock and is unable to support the requested PWM period. > > Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by > updating the parent clock for the PWM to be the PLL_P. > > Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20 > Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20 > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30 > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3 > --- Applied to clk-next
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f7405a58877e..73303458e886 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1166,6 +1166,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 }, + { TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 }, /* must be the last entry */ { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index a9d4efcef2d4..6c46592d794e 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1330,6 +1330,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, + { TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 }, /* must be the last entry */ { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 8a4514f6d503..422d78247553 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1044,6 +1044,7 @@ static struct tegra_clk_init_table init_table[] = { { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, + { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, /* must be the last entry */ { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 499f999e91e1..a3488aaac3f7 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3597,6 +3597,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 }, { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 }, + { TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 }, /* This MUST be the last entry. */ { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 168c07d5a5f2..60f1534711f1 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[] = { { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, };
Commit 8c193f4714df ("pwm: tegra: Optimize period calculation") updated the period calculation in the Tegra PWM driver and now returns an error if the period requested is less than minimum period supported. This is breaking PWM support on various Tegra platforms. For example, on the Tegra210 Jetson Nano platform this is breaking the PWM fan support and probing the PWM fan driver now fails ... pwm-fan pwm-fan: Failed to configure PWM: -22 pwm-fan: probe of pwm-fan failed with error -22 The problem is that the default parent clock for the PWM on Tegra210 is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20 Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3 --- Changes since V2: - Added fix for Tegra114 - Added tested-by info from various testers (sent directly to me) Changes since V1: - Added fixes for Tegra20 and Tegra30 drivers/clk/tegra/clk-tegra114.c | 1 + drivers/clk/tegra/clk-tegra124.c | 1 + drivers/clk/tegra/clk-tegra20.c | 1 + drivers/clk/tegra/clk-tegra210.c | 1 + drivers/clk/tegra/clk-tegra30.c | 1 + 5 files changed, 5 insertions(+)