| Message ID | 20221003101555.25458-1-jonathanh@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | clk: tegra: Fix Tegra210 PWM parent clock | expand |
On 03/10/2022 11:15, Jon Hunter wrote: > Commit 8c193f4714df ("pwm: tegra: Optimize period calculation") updated > the period calculation in the Tegra PWM driver and now returns an error > if the period requested is less than minimum period supported. This is > breaking PWM fan support on the Tegra210 Jetson Nano platform and > probing the PWM fan driver now fails ... > > pwm-fan pwm-fan: Failed to configure PWM: -22 > pwm-fan: probe of pwm-fan failed with error -22 > > The problem is that the default parent clock for the PWM on Tegra210 is > a 32kHz clock and is unable to support the requested PWM period. Fix > this by updating the parent clock for the PWM to be the PLL_P which > operates at 48MHz. > > Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> I have sent a V2 on this to fix the PWM support for some other Tegra devices. Jon
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 499f999e91e1..a3488aaac3f7 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3597,6 +3597,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 }, { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 }, + { TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 }, /* This MUST be the last entry. */ { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, };
Commit 8c193f4714df ("pwm: tegra: Optimize period calculation") updated the period calculation in the Tegra PWM driver and now returns an error if the period requested is less than minimum period supported. This is breaking PWM fan support on the Tegra210 Jetson Nano platform and probing the PWM fan driver now fails ... pwm-fan pwm-fan: Failed to configure PWM: -22 pwm-fan: probe of pwm-fan failed with error -22 The problem is that the default parent clock for the PWM on Tegra210 is a 32kHz clock and is unable to support the requested PWM period. Fix this by updating the parent clock for the PWM to be the PLL_P which operates at 48MHz. Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> --- drivers/clk/tegra/clk-tegra210.c | 1 + 1 file changed, 1 insertion(+)