| Message ID | 20220928062731.18032-1-vidyas@nvidia.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [V1] arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllers | expand |
Hi Rob / Thierry, Any comments on this patch? Thanks, Vidya Sagar On 9/28/2022 11:57 AM, Vidya Sagar wrote: > commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against > hardware constraints") exposes an issue with the existing partitioning of > the aperture space where the Prefetchable apertures of controllers > C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint. > This patch makes sure that the Prefetchable region doesn't spill over > the 32GB boundary. > > Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index 0170bfa8a467..9b43a0b0d775 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -1965,7 +1965,7 @@ > > bus-range = <0x0 0xff>; > > - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ > + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ > <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ > <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ > > @@ -2336,7 +2336,7 @@ > > bus-range = <0x0 0xff>; > > - ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ > + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ > <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ > <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ > > @@ -2442,7 +2442,7 @@ > > bus-range = <0x0 0xff>; > > - ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ > + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ > <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ > <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ > >
On Wed, Sep 28, 2022 at 11:57:31AM +0530, Vidya Sagar wrote: > commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against > hardware constraints") exposes an issue with the existing partitioning of > the aperture space where the Prefetchable apertures of controllers > C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint. > This patch makes sure that the Prefetchable region doesn't spill over > the 32GB boundary. > > Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Applied, thanks. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..9b43a0b0d775 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1965,7 +1965,7 @@ bus-range = <0x0 0xff>; - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -2336,7 +2336,7 @@ bus-range = <0x0 0xff>; - ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -2442,7 +2442,7 @@ bus-range = <0x0 0xff>; - ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against hardware constraints") exposes an issue with the existing partitioning of the aperture space where the Prefetchable apertures of controllers C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint. This patch makes sure that the Prefetchable region doesn't spill over the 32GB boundary. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)