Message ID | 20220926115038.24727-10-vidyas@nvidia.com |
---|---|
State | Superseded |
Headers | show
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Mon, 26 Sep 2022 04:51:45 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 26 Sep 2022 04:51:45 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Mon, 26 Sep 2022 04:51:40 -0700 From: Vidya Sagar <vidyas@nvidia.com> To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>, <mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>, <ffclaire1224@gmail.com> CC: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com> Subject: [PATCH V2 9/9] PCI: tegra194: Calibrate P2U for endpoint mode Date: Mon, 26 Sep 2022 17:20:38 +0530 Message-ID: <20220926115038.24727-10-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220926115038.24727-1-vidyas@nvidia.com> References: <20220926115038.24727-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT038:EE_|CH2PR12MB4969:EE_ X-MS-Office365-Filtering-Correlation-Id: d03c46b7-4764-4a8a-dba3-08da9fb582d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Series |
Enhancements to pcie-tegra194 driver
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expand
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diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 3e4868ab8416..cfe32a98b2f3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1078,6 +1078,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) ret = phy_power_on(pcie->phys[i]); if (ret < 0) goto phy_exit; + + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + phy_calibrate(pcie->phys[i]); } return 0;
Calibrate P2U for endpoint to request UPHY PLL rate change to Gen1 during initialization. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ 1 file changed, 3 insertions(+)