diff mbox series

[v2] clk: tegra: Add missing reset deassertion

Message ID 20220429125843.neqitcrxc7ntjclk@diogo-laptop
State Accepted
Headers show
Series [v2] clk: tegra: Add missing reset deassertion | expand

Commit Message

Diogo Ivo April 29, 2022, 12:58 p.m. UTC 
Commit 4782c0a5dd88e3797426e08c5c437e95a3156631 ("clk: tegra: Don't
deassert reset on enabling clocks") removed deassertion of reset lines
when enabling peripheral clocks. This breaks the initialization of the
DFLL driver which relied on this behaviour.

Fix this problem by adding explicit deassert/assert requests to the
driver and the corresponding reset to the DT. Tested on Google Pixel C.

Cc: stable@vger.kernel.org
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
---
Changes in v2:
 - Changed reset getter to the optional variant

 arch/arm64/boot/dts/nvidia/tegra210.dtsi |  5 +++--
 drivers/clk/tegra/clk-dfll.c             | 12 ++++++++++++
 2 files changed, 15 insertions(+), 2 deletions(-)

Comments

Thierry Reding May 4, 2022, 9:24 a.m. UTC | #1 
On Fri, Apr 29, 2022 at 01:58:43PM +0100, Diogo Ivo wrote:
> Commit 4782c0a5dd88e3797426e08c5c437e95a3156631 ("clk: tegra: Don't
> deassert reset on enabling clocks") removed deassertion of reset lines
> when enabling peripheral clocks. This breaks the initialization of the
> DFLL driver which relied on this behaviour.
> 
> Fix this problem by adding explicit deassert/assert requests to the
> driver and the corresponding reset to the DT. Tested on Google Pixel C.
> 
> Cc: stable@vger.kernel.org
> Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
> Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
> ---
> Changes in v2:
>  - Changed reset getter to the optional variant
> 
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi |  5 +++--
>  drivers/clk/tegra/clk-dfll.c             | 12 ++++++++++++
>  2 files changed, 15 insertions(+), 2 deletions(-)

I've applied this, but in the process split it up into two: one patch
for the clock driver and another for the device tree changes. For future
patches, please keep in mind that driver and device tree changes should
always be separate.

Thanks,
Thierry
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 218a2b32200f..4f0e51f1a343 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1366,8 +1366,9 @@  dfll: clock@70110000 {
 			 <&tegra_car TEGRA210_CLK_DFLL_REF>,
 			 <&tegra_car TEGRA210_CLK_I2C5>;
 		clock-names = "soc", "ref", "i2c";
-		resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
-		reset-names = "dvco";
+		resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
+			 <&tegra_car 155>;
+		reset-names = "dvco", "dfll";
 		#clock-cells = <0>;
 		clock-output-names = "dfllCPU_out";
 		status = "disabled";
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 6144447f86c6..62238dca9a53 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -271,6 +271,7 @@  struct tegra_dfll {
 	struct clk			*ref_clk;
 	struct clk			*i2c_clk;
 	struct clk			*dfll_clk;
+	struct reset_control		*dfll_rst;
 	struct reset_control		*dvco_rst;
 	unsigned long			ref_rate;
 	unsigned long			i2c_clk_rate;
@@ -1464,6 +1465,7 @@  static int dfll_init(struct tegra_dfll *td)
 		return -EINVAL;
 	}
 
+	reset_control_deassert(td->dfll_rst);
 	reset_control_deassert(td->dvco_rst);
 
 	ret = clk_prepare(td->ref_clk);
@@ -1509,6 +1511,7 @@  static int dfll_init(struct tegra_dfll *td)
 	clk_unprepare(td->ref_clk);
 
 	reset_control_assert(td->dvco_rst);
+	reset_control_assert(td->dfll_rst);
 
 	return ret;
 }
@@ -1530,6 +1533,7 @@  int tegra_dfll_suspend(struct device *dev)
 	}
 
 	reset_control_assert(td->dvco_rst);
+	reset_control_assert(td->dfll_rst);
 
 	return 0;
 }
@@ -1548,6 +1552,7 @@  int tegra_dfll_resume(struct device *dev)
 {
 	struct tegra_dfll *td = dev_get_drvdata(dev);
 
+	reset_control_deassert(td->dfll_rst);
 	reset_control_deassert(td->dvco_rst);
 
 	pm_runtime_get_sync(td->dev);
@@ -1951,6 +1956,12 @@  int tegra_dfll_register(struct platform_device *pdev,
 
 	td->soc = soc;
 
+	td->dfll_rst = devm_reset_control_get_optional(td->dev, "dfll");
+	if (IS_ERR(td->dfll_rst)) {
+		dev_err(td->dev, "couldn't get dfll reset\n");
+		return PTR_ERR(td->dfll_rst);
+	}
+
 	td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
 	if (IS_ERR(td->dvco_rst)) {
 		dev_err(td->dev, "couldn't get dvco reset\n");
@@ -2087,6 +2098,7 @@  struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
 	clk_unprepare(td->i2c_clk);
 
 	reset_control_assert(td->dvco_rst);
+	reset_control_assert(td->dfll_rst);
 
 	return td->soc;
 }