| Message ID | 20220425075036.30098-4-amhetre@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | memory: tegra: Add MC channels and error logging | expand |
On Mon, 25 Apr 2022 13:20:35 +0530, Ashish Mhetre wrote:
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/
memory-controller@2c00000: reg: [[0, 46137344, 0, 720896]] is too short
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dtb
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dtb
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb
memory-controller@2c00000: reg: [[46137344, 1048576], [45613056, 262144], [24117248, 1048576]] is too short
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dtb
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dtb
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dtb
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dtb
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dtb
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dtb
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dtb
memory-controller@2c00000: 'reg-names' is a required property
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dtb
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dtb
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dtb
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dtb
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dtb
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dtb
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dtb
On Mon, 25 Apr 2022 13:20:35 +0530, Ashish Mhetre wrote: > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 13c4c82fd0d3..c7cfa6c2cd81 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6 + maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items: @@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties: @@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties: @@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-names - interrupts - "#address-cells" - "#size-cells" @@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>;
From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each. There is 1 reg item for memory controller stream-id registers. So update the reg minItems and maxItems accordingly in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items. ABI change due to new bindings is intended but backward compatibility is preserved in driver. Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> --- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-)