| Message ID | 20191003205033.98381-1-swarren@wwwdotorg.org |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [V3,1/4] clk: tegra: mark fuse clock as critical | expand |
On 10/3/19 2:50 PM, Stephen Warren wrote: > From: Stephen Warren <swarren@nvidia.com> > > For a little over a year, U-Boot on Tegra124 has configured the flow > controller to perform automatic RAM re-repair on off->on power transitions > of the CPU rail1]. This is mandatory for correct operation of Tegra124. > However, RAM re-repair relies on certain clocks, which the kernel must > enable and leave running. The fuse clock is one of those clocks. Mark this > clock as critical so that LP1 power mode (system suspend) operates > correctly. > > [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Thierry, this series doesn't seem to be applied yet; could you please take a look? Thanks.
On Thu, Oct 03, 2019 at 02:50:30PM -0600, Stephen Warren wrote: > From: Stephen Warren <swarren@nvidia.com> > > For a little over a year, U-Boot on Tegra124 has configured the flow > controller to perform automatic RAM re-repair on off->on power transitions > of the CPU rail1]. This is mandatory for correct operation of Tegra124. > However, RAM re-repair relies on certain clocks, which the kernel must > enable and leave running. The fuse clock is one of those clocks. Mark this > clock as critical so that LP1 power mode (system suspend) operates > correctly. > > [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair > > Reported-by: Jonathan Hunter <jonathanh@nvidia.com> > Cc: stable@vger.kernel.org > Signed-off-by: Stephen Warren <swarren@nvidia.com> > --- > v3: Added comment to the clock table entry indicating why the clock is > critical. > v2: Set CRITICAL flag on the clock, rather than enabling it in > tegra124_init_table[]. > --- > drivers/clk/tegra/clk-tegra-periph.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) Applied to for-5.6/clk, thanks. Thierry
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 1ed85f120a1b..49b9f2f85bad 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -785,7 +785,11 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), + /* + * Critical for RAM re-repair operation, which must occur on resume + * from LP1 system suspend and as part of CCPLEX cluster switching. + */ + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),