From patchwork Wed Jan 9 01:22:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 1022264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="hGGB3J4t"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43ZBFt2nlNz9sMM for ; Wed, 9 Jan 2019 12:22:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728835AbfAIBW4 (ORCPT ); Tue, 8 Jan 2019 20:22:56 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:2690 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728253AbfAIBW4 (ORCPT ); Tue, 8 Jan 2019 20:22:56 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 08 Jan 2019 17:22:28 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 08 Jan 2019 17:22:52 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 08 Jan 2019 17:22:52 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Jan 2019 01:22:51 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 9 Jan 2019 01:22:51 +0000 Received: from localhost.localdomain (Not Verified[10.19.225.143]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 08 Jan 2019 17:22:51 -0800 From: Mark Zhang To: CC: Mark Zhang Subject: [PATCH] Add the Tegra210 p2894(a.k.a Darcy) board Date: Wed, 9 Jan 2019 09:22:41 +0800 Message-ID: <20190109012241.6616-1-markz@nvidia.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546996948; bh=OUtHBzDWb3/sQNzgpR4Kod8zZXvwGeppbhf3BpUL1+E=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=hGGB3J4tjHzueWLHFQ2A1e7uUm4neUs5Y8SLtWSaK33ILsUeKI+4CaULzchwK1G4a iKBce6Z0Q9NBu1jzEK7eDUqqqnYoUq83uwna+PWgYmpCTF6LPg/hY3WBw1tTdDw9NY ExsEbKI8AW85piDZvLzrQHB2s4JsU5CP+yZV2tsWwIuALy/tBflOutQYDISzkMl2L8 PTzuoDwcxLzQbhmXtp5ZwIQg4DqMPBchaiTnNINNsPNcNBXaYNuDPgJkcWW66e62P9 9E+J7FOIEGLYAVwAXm1Mq67A2kyES4peYZUrDLJiu+HBXxZshTEocJEXOwkMBZaeyV 58RGzzZpyvAFQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 Darcy is the name for the NVIDIA Shield TV platform. Signed-off-by: Mark Zhang --- configs/tegra210-p2894.board | 173 +++++++++++++++++++++++++++++++++++ csv-to-board.py | 6 ++ 2 files changed, 179 insertions(+) create mode 100644 configs/tegra210-p2894.board diff --git a/configs/tegra210-p2894.board b/configs/tegra210-p2894.board new file mode 100644 index 000000000000..4d19af7b7250 --- /dev/null +++ b/configs/tegra210-p2894.board @@ -0,0 +1,173 @@ +soc = 'tegra210' + +pins = ( + #pin, mux, gpio_init, pull, tri, e_inp, od, e_io_hv + ('aud_mclk_pbb0', 'rsvd1', None, 'down', True, False, False, False), + ('dvfs_pwm_pbb1', 'cldvfs', None, 'none', True, False, False, False), + ('dvfs_clk_pbb2', None, 'out0', 'none', False, False, False, False), + ('gpio_x1_aud_pbb3', 'rsvd0', None, 'down', True, False, False, False), + ('gpio_x3_aud_pbb4', 'rsvd0', None, 'down', True, False, False, False), + ('dap1_din_pb1', 'rsvd1', None, 'down', True, False, False, False), + ('dap1_dout_pb2', 'rsvd1', None, 'down', True, False, False, False), + ('dap1_fs_pb0', 'rsvd1', None, 'down', True, False, False, False), + ('dap1_sclk_pb3', 'rsvd1', None, 'down', True, False, False, False), + ('spi2_mosi_pb4', 'rsvd2', None, 'down', True, False, False, False), + ('spi2_miso_pb5', 'rsvd2', None, 'down', True, False, False, False), + ('spi2_sck_pb6', 'rsvd2', None, 'down', True, False, False, False), + ('spi2_cs0_pb7', 'rsvd2', None, 'down', True, False, False, False), + ('spi2_cs1_pdd0', 'rsvd1', None, 'down', True, False, False, False), + ('dmic1_clk_pe0', 'rsvd2', None, 'down', True, False, False, False), + ('dmic1_dat_pe1', 'rsvd2', None, 'down', True, False, False, False), + ('dmic2_clk_pe2', 'rsvd2', None, 'down', True, False, False, False), + ('dmic2_dat_pe3', 'rsvd2', None, 'down', True, False, False, False), + ('dmic3_clk_pe4', None, 'out0', 'none', False, False, False, False), + ('dmic3_dat_pe5', 'rsvd2', None, 'down', True, False, False, False), + ('pe6', None, 'in', 'down', False, True, False, False), + ('pe7', 'pwm3', None, 'none', False, False, False, False), + ('gen3_i2c_scl_pf0', 'i2c3', None, 'none', False, True, False, False), + ('gen3_i2c_sda_pf1', 'i2c3', None, 'none', False, True, False, False), + ('cam_i2c_scl_ps2', 'rsvd2', None, 'down', True, False, False, False), + ('cam_i2c_sda_ps3', 'rsvd2', None, 'down', True, False, False, False), + ('cam1_mclk_ps0', 'rsvd1', None, 'down', True, False, False, False), + ('cam2_mclk_ps1', 'rsvd1', None, 'down', True, False, False, False), + ('cam_rst_ps4', 'rsvd1', None, 'down', True, False, False, False), + ('cam_af_en_ps5', 'rsvd2', None, 'down', True, False, False, False), + ('cam_flash_en_ps6', 'rsvd2', None, 'down', True, False, False, False), + ('cam1_pwdn_ps7', 'rsvd1', None, 'down', True, False, False, False), + ('cam2_pwdn_pt0', 'rsvd1', None, 'down', True, False, False, False), + ('cam1_strobe_pt1', 'rsvd1', None, 'down', True, False, False, False), + ('pex_l0_clkreq_n_pa1', 'pe0', None, 'none', False, True, False, True), + ('pex_l0_rst_n_pa0', 'rsvd1', None, 'down', True, False, False, False), + ('pex_l1_clkreq_n_pa4', 'pe1', None, 'none', False, True, False, True), + ('pex_l1_rst_n_pa3', 'pe1', None, 'none', False, False, False, True), + ('pex_wake_n_pa2', 'pe', None, 'none', False, True, False, True), + ('sata_led_active_pa5', None, 'in', 'up', False, True, False, False), + ('pa6', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc1_clk_pm0', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc1_cmd_pm1', 'rsvd2', None, 'down', True, False, False, False), + ('sdmmc1_dat0_pm5', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc1_dat1_pm4', 'rsvd2', None, 'down', True, False, False, False), + ('sdmmc1_dat2_pm3', 'rsvd2', None, 'down', True, False, False, False), + ('sdmmc1_dat3_pm2', 'rsvd2', None, 'down', True, False, False, False), + ('sdmmc3_clk_pp0', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc3_cmd_pp1', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc3_dat0_pp5', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc3_dat1_pp4', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc3_dat2_pp3', 'rsvd1', None, 'down', True, False, False, False), + ('sdmmc3_dat3_pp2', 'rsvd1', None, 'down', True, False, False, False), + ('als_prox_int_px3', 'rsvd0', None, 'down', True, False, False, False), + ('temp_alert_px4', None, 'in', 'up', False, True, False, False), + ('motion_int_px2', 'rsvd0', None, 'down', True, False, False, False), + ('touch_rst_pv6', 'rsvd0', None, 'down', True, False, False, False), + ('touch_clk_pv7', 'rsvd1', None, 'down', True, False, False, False), + ('touch_int_px1', 'rsvd0', None, 'down', True, False, False, False), + ('modem_wake_ap_px0', 'rsvd0', None, 'down', True, False, False, False), + ('shutdown', 'shutdown', None, 'none', False, False, False, False), + ('button_power_on_px5', 'rsvd0', None, 'down', True, False, False, False), + ('button_vol_up_px6', None, 'in', 'up', False, True, False, False), + ('button_vol_down_px7', None, 'in', 'up', False, True, False, False), + ('button_slide_sw_py0', 'rsvd0', None, 'down', True, False, False, False), + ('button_home_py1', None, 'in', 'up', False, True, False, False), + ('lcd_te_py2', 'rsvd1', None, 'down', True, False, False, False), + ('lcd_bl_pwm_pv0', 'pwm0', None, 'none', False, False, False, False), + ('lcd_bl_en_pv1', 'rsvd0', None, 'down', True, False, False, False), + ('lcd_rst_pv2', 'rsvd0', None, 'down', True, False, False, False), + ('lcd_gpio1_pv3', 'rsvd1', None, 'down', True, False, False, False), + ('lcd_gpio2_pv4', 'pwm1', None, 'none', False, False, False, False), + ('ap_ready_pv5', 'rsvd0', None, 'down', True, False, False, False), + ('pwr_i2c_scl_py3', 'i2cpmu', None, 'none', False, True, False, False), + ('pwr_i2c_sda_py4', 'i2cpmu', None, 'none', False, True, False, False), + ('clk_32k_in', 'clk', None, 'none', False, True, False, False), + ('clk_32k_out_py5', 'rsvd2', None, 'down', True, False, False, False), + ('pz0', None, 'in', 'up', False, True, False, False), + ('pz1', 'rsvd2', None, 'down', True, False, False, False), + ('pz2', 'rsvd2', None, 'down', True, False, False, False), + ('pz3', 'rsvd1', None, 'down', True, False, False, False), + ('pz4', 'rsvd1', None, 'down', True, False, False, False), + ('pz5', 'soc', None, 'up', False, True, False, False), + ('clk_req', 'rsvd1', None, 'down', True, False, False, False), + ('core_pwr_req', 'core', None, 'none', False, False, False, False), + ('cpu_pwr_req', 'rsvd1', None, 'down', True, False, False, False), + ('pwr_int_n', 'pmi', None, 'up', False, True, False, False), + ('dap4_din_pj5', 'rsvd1', None, 'down', True, False, False, False), + ('dap4_dout_pj6', 'rsvd1', None, 'down', True, False, False, False), + ('dap4_fs_pj4', 'rsvd1', None, 'down', True, False, False, False), + ('dap4_sclk_pj7', 'rsvd1', None, 'down', True, False, False, False), + ('gen1_i2c_scl_pj1', 'i2c1', None, 'none', False, True, False, False), + ('gen1_i2c_sda_pj0', 'i2c1', None, 'none', False, True, False, False), + ('gen2_i2c_scl_pj2', 'i2c2', None, 'none', False, True, False, True), + ('gen2_i2c_sda_pj3', 'i2c2', None, 'none', False, True, False, True), + ('uart2_tx_pg0', None, 'in', 'none', False, True, False, False), + ('uart2_rx_pg1', 'uartb', None, 'down', True, False, False, False), + ('uart2_rts_pg2', 'rsvd2', None, 'down', True, False, False, False), + ('uart2_cts_pg3', 'rsvd2', None, 'down', True, False, False, False), + ('uart1_tx_pu0', 'uarta', None, 'none', False, False, False, False), + ('uart1_rx_pu1', 'uarta', None, 'up', False, True, False, False), + ('uart1_rts_pu2', 'uarta', None, 'none', False, False, False, False), + ('uart1_cts_pu3', 'uarta', None, 'up', False, True, False, False), + ('jtag_rtck', 'jtag', None, 'none', False, False, False, False), + ('pk0', 'rsvd2', None, 'down', True, False, False, False), + ('pk1', 'rsvd2', None, 'down', True, False, False, False), + ('pk2', 'rsvd2', None, 'down', True, False, False, False), + ('pk3', 'rsvd2', None, 'down', True, False, False, False), + ('pk4', 'rsvd1', None, 'down', True, False, False, False), + ('pk5', 'rsvd1', None, 'down', True, False, False, False), + ('pk6', 'rsvd1', None, 'down', True, False, False, False), + ('pk7', 'rsvd1', None, 'down', True, False, False, False), + ('pl0', 'rsvd0', None, 'down', True, False, False, False), + ('pl1', 'rsvd1', None, 'down', True, False, False, False), + ('spi1_mosi_pc0', 'rsvd1', None, 'down', True, False, False, False), + ('spi1_miso_pc1', 'rsvd1', None, 'down', True, False, False, False), + ('spi1_sck_pc2', 'rsvd1', None, 'down', True, False, False, False), + ('spi1_cs0_pc3', 'rsvd1', None, 'down', True, False, False, False), + ('spi1_cs1_pc4', 'rsvd1', None, 'down', True, False, False, False), + ('spi4_mosi_pc7', 'rsvd1', None, 'down', True, False, False, False), + ('spi4_miso_pd0', 'rsvd1', None, 'down', True, False, False, False), + ('spi4_sck_pc5', 'rsvd1', None, 'down', True, False, False, False), + ('spi4_cs0_pc6', 'rsvd1', None, 'down', True, False, False, False), + ('uart3_tx_pd1', 'rsvd2', None, 'down', True, False, False, False), + ('uart3_rx_pd2', 'rsvd2', None, 'down', True, False, False, False), + ('uart3_rts_pd3', 'rsvd2', None, 'down', True, False, False, False), + ('uart3_cts_pd4', None, 'out0', 'none', False, False, False, False), + ('wifi_en_ph0', None, 'out0', 'none', False, False, False, False), + ('wifi_rst_ph1', 'rsvd0', None, 'down', True, False, False, False), + ('wifi_wake_ap_ph2', None, 'in', 'up', False, True, False, False), + ('ap_wake_bt_ph3', None, 'out0', 'none', False, False, False, False), + ('bt_rst_ph4', None, 'out0', 'none', False, False, False, False), + ('bt_wake_ap_ph5', None, 'in', 'up', False, True, False, False), + ('ph6', 'rsvd0', None, 'down', True, False, False, False), + ('ap_wake_nfc_ph7', 'rsvd0', None, 'down', True, False, False, False), + ('nfc_en_pi0', 'rsvd0', None, 'down', True, False, False, False), + ('nfc_int_pi1', 'rsvd0', None, 'down', True, False, False, False), + ('gps_en_pi2', 'rsvd0', None, 'down', True, False, False, False), + ('gps_rst_pi3', 'rsvd0', None, 'down', True, False, False, False), + ('uart4_tx_pi4', 'uartd', None, 'none', False, False, False, False), + ('uart4_rx_pi5', 'uartd', None, 'none', False, True, False, False), + ('uart4_rts_pi6', 'uartd', None, 'none', False, False, False, False), + ('uart4_cts_pi7', 'uartd', None, 'none', False, True, False, False), + ('qspi_io0_pee2', 'rsvd1', None, 'down', True, False, False, False), + ('qspi_io1_pee3', 'rsvd1', None, 'down', True, False, False, False), + ('qspi_sck_pee0', 'rsvd1', None, 'down', True, False, False, False), + ('qspi_cs_n_pee1', 'rsvd1', None, 'down', True, False, False, False), + ('qspi_io2_pee4', 'rsvd1', None, 'down', True, False, False, False), + ('qspi_io3_pee5', 'rsvd1', None, 'down', True, False, False, False), + ('dap2_din_paa2', 'i2s2', None, 'none', False, True, False, False), + ('dap2_dout_paa3', 'i2s2', None, 'none', False, True, False, False), + ('dap2_fs_paa0', 'i2s2', None, 'none', False, True, False, False), + ('dap2_sclk_paa1', 'i2s2', None, 'none', False, True, False, False), + ('pcc7', None, 'out0', 'none', False, False, False, False), + ('spdif_out_pcc2', 'rsvd1', None, 'down', True, False, False, False), + ('spdif_in_pcc3', 'rsvd1', None, 'down', True, False, False, False), + ('usb_vbus_en0_pcc4', 'usb', None, 'none', False, True, False, True), + ('usb_vbus_en1_pcc5', 'usb', None, 'none', False, True, False, True), + ('dp_hpd0_pcc6', 'rsvd1', None, 'down', True, False, False, False), + ('hdmi_int_dp_hpd_pcc1', None, 'in', 'down', False, True, False, False), + ('hdmi_cec_pcc0', 'cec', None, 'none', False, True, False, True), +) + +drive_groups = ( +) + +mipi_pad_ctrl_groups = ( + #pin, mux +) diff --git a/csv-to-board.py b/csv-to-board.py index ff0fcba007d3..96d1ad8fc220 100755 --- a/csv-to-board.py +++ b/csv-to-board.py @@ -96,6 +96,12 @@ supported_boards = { 'rsvd_base': 0, 'soc': 'tegra210', }, + 'tegra210-p2894': { + # T210_customer_pinmux.xlsm + 'filename': 'csv/tegra210-p2894.csv', + 'rsvd_base': 0, + 'soc': 'tegra210', + }, 'venice2': { # Venice2_T124_customer_pinmux_based_on_P4_rev47_2013-07-12.xlsm worksheet Customer_Configuration (0-based rsvd) 'filename': 'nv-internal-data/Venice2_T124_customer_pinmux_based_on_P4_rev47_2013-07-12.csv',