From patchwork Mon Dec 10 09:43:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 1010340 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="duMigvR0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43CypH36yYz9s2P for ; Mon, 10 Dec 2018 20:44:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726638AbeLJJoX (ORCPT ); Mon, 10 Dec 2018 04:44:23 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:13985 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726610AbeLJJoW (ORCPT ); Mon, 10 Dec 2018 04:44:22 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Dec 2018 01:44:19 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 10 Dec 2018 01:44:21 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 10 Dec 2018 01:44:21 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Dec 2018 09:44:20 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 10 Dec 2018 09:44:20 +0000 Received: from localhost.localdomain (Not Verified[10.19.225.143]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Dec 2018 01:44:20 -0800 From: Mark Zhang To: , , CC: Mark Zhang Subject: [PATCH 1/5] arm64: tegra: Add support for NVIDIA Shield TV Date: Mon, 10 Dec 2018 17:43:54 +0800 Message-ID: <20181210094358.3241-2-markz@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181210094358.3241-1-markz@nvidia.com> References: <20181210094358.3241-1-markz@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544435059; bh=SXZn64nt2h0dGoB+P1q0SXy53zPDLFEh7viacCtD6GQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=duMigvR0OWrAQ0gp966R2HQT1JWPO3BowbRRT9SODu+1e/Cn9lTIMqq8hZ+1UyaXp bCN6bWRTjKBMSqYszrP7DLWM0ciBKQuNBDnUEfs7D8pQVWF9i+2DsTSLxa2LTTmmu2 /wGGLPoq0sq+WnOCa3hAsPNUceuXRzrQVapjy6lkVzMQ2X/gDcipeLEIjPL+JY5L8B sBFD/MFhBwaZbzfgOzILQsYYRyqZez4zkLXGrDUPb7hhwwxlE/CvvDJboBi8qwiFu3 ULHtZfBgyOguwEiKrIKDfZOSD++yRHlCEj/SLcCFz4m/8cz+H4cV3N5nKnpszKsBsS +2dcziWXEnj8g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add initial device-tree support for NVIDIA Shield TV (a.k.a. Darcy) based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. Signed-off-by: Mark Zhang --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../dts/nvidia/tegra210-p2894-0050-a08.dts | 10 +++ .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 77 +++++++++++++++++++ 3 files changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 7c13d7df484e..6b8ab5568481 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb +dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts new file mode 100644 index 000000000000..82bc6b1e0c5c --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra210.dtsi" +#include "tegra210-p2894.dtsi" + +/ { + model = "NVIDIA Shield TV"; + compatible = "nvidia,darcy", "nvidia,foster-e", "nvidia,tegra210"; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi new file mode 100644 index 000000000000..ac52286ab9ab --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra210.dtsi" + +/ { + aliases { + serial0 = &uarta; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + serial@70006000 { + status = "okay"; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + status = "okay"; + }; + + sdhci@700b0600 { + bus-width = <8>; + non-removable; + status = "okay"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +};