From patchwork Sat Feb 10 01:38:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZVN3cYYz9rxj for ; Sat, 10 Feb 2018 12:44:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752528AbeBJBoF (ORCPT ); Fri, 9 Feb 2018 20:44:05 -0500 Received: from mout.perfora.net ([74.208.4.197]:37797 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752172AbeBJBoD (ORCPT ); Fri, 9 Feb 2018 20:44:03 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0MCrG1-1ebHi9250V-009gKo; Sat, 10 Feb 2018 02:38:23 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: dts: tegra: apalis-tk1: hog group for ethernet, pcie, reset gpios Date: Sat, 10 Feb 2018 02:38:04 +0100 Message-Id: <20180210013806.28496-5-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:M3fmOvleO9n6WsFexiZLkA2W5ROjyWQlO+xNbgadPe6J7NQNF6C ngsQ7WXlMjlHjpM55ZQGY0xVlSxDFltb5ZaSYt43h8EsfwOIuPnsPyI+/7ypBaOTFkT5tb/ R7HBJIEmN+3EoH4lPwaTWOeH71X6AIFQAklqK1osOu0VqVJdI6rn7dAGpDayiugHksVJ1wH /vAph89vAtXPaed337Q5g== X-UI-Out-Filterresults: notjunk:1; V01:K0:1vWfnneh4Lg=:j0CLIPZtbBrrURrtBi4lEM ePXWQlRp3Rw3d8S8IxZrno68B4zRelg/GojWL/tk/L+7ENoMBjv7cXp+BjKl934ei5jvEldfv qWbN91CcdndZ/jZNTC2g4AiU+151o8Qjx9IGBaRUR6ufR7VFepBicLAp67/nNSWkQE8hORMB/ S3Lw5qRKqkDB2Lyzgg8kAAPr+BFzU7b/UbWegkoiWuYqVaWL2rvz46S7Ikrq6lKEx9oeGatYP yJVrBo6YhSUeKzvdIP5rP8oNH9ooHs4xXs5ZvR2RCCkU5LyryuR2PjzjT4r3jKS403BN2WtRr /GzPFpZLXXwhIDrICtfQbgbP5X5fnSFmFmTY5MWMIVHKLTdiW0/NE/0i4McsYQPciIcViXdlw KkHo5CVzD8HkJjiN9MvAhCL6jgylPESuqZgI+Tm4DDsCdpvcv3TR+aayO1fmVHeDWfA3MS5ft U0qvlFc6kz8bJONe58v7JGn7UWaMjfb+8/Mo6QnHs0fWlQcACURkAh8jY/CwYC0EwxPkxN0pJ K8vhDI0NtEN0N7GvSsnnINEeslC94HUkMdca6oPGXbLkeS9XNI8T3e6FRxE8ZcpjzTNrMo/xO 0cJhMKR+I7ab6aH20wIRQL3JG1c4WLK4DZmZ7AUOwz5leTOhJwyfq/iELGpC0+8egpQd+5DDf /QG87ACKzOhoevBI0pgT4Zbva+G+pfzFv/s6iYhhcvTM/TjbfUWJdjUqOr/uFn/Hbx7mCvED6 S7yY0xg/iYhhSf+N7WE5vifJHn9KVMMw7iQ1IA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler The Apalis TK1 module uses some dedicated GPIOs as I210 gigabit Ethernet controller reset and to control RESET_MOCI aka reset module output carrier input on MXM3 pin 26. The Apalis Evaluation Board furthermore uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 10 ++++++++++ arch/arm/boot/dts/tegra124-apalis.dtsi | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index af6c566e8ac4..f1010cefb993 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -275,3 +275,13 @@ vin-supply = <®_5v0>; }; }; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex_perst_n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 44c31176ce90..b7648ce4565d 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2070,3 +2070,21 @@ }; }; }; + +&gpio { + /* I210 Gigabit Ethernet Controller Reset */ + lan_reset_n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset_moci_ctrl { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; +};