From patchwork Mon Jun 27 09:02:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 640867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rdNJs3YThz9sBm for ; Mon, 27 Jun 2016 19:03:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750736AbcF0JDk (ORCPT ); Mon, 27 Jun 2016 05:03:40 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1224 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752088AbcF0JCx (ORCPT ); Mon, 27 Jun 2016 05:02:53 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 27 Jun 2016 02:02:21 -0700 Received: from HQMAIL107.nvidia.com ([172.20.187.13]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 27 Jun 2016 02:01:44 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 27 Jun 2016 02:01:44 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Mon, 27 Jun 2016 09:02:53 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Mon, 27 Jun 2016 09:02:52 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Mon, 27 Jun 2016 09:02:52 +0000 Received: from jlo-ubuntu64.nvidia.com (Not Verified[10.19.108.111]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Mon, 27 Jun 2016 02:02:51 -0700 From: Joseph Lo To: Stephen Warren , Thierry Reding , Alexandre Courbot CC: , , "Rob Herring" , Mark Rutland , "Peter De Schrijver" , Matthew Longnecker , , Jassi Brar , , Catalin Marinas , Will Deacon , Joseph Lo Subject: [PATCH 08/10] arm64: dts: tegra: Add Tegra186 support Date: Mon, 27 Jun 2016 17:02:46 +0800 Message-ID: <20160627090248.23621-9-josephl@nvidia.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160627090248.23621-1-josephl@nvidia.com> References: <20160627090248.23621-1-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This adds the initial support of Tegra186 SoC, which can help to bring up the debug console and initrd for further developing. Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra186.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi new file mode 100644 index 000000000000..bed30f30bb0b --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -0,0 +1,77 @@ +#include +#include + +/ { + compatible = "nvidia,tegra186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + uarta: serial@03100000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03100000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@03881000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x03881000 0x0 0x1000>, + <0x0 0x03882000 0x0 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + hsp_top: hsp@03c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + nvidia,hsp-function = ; + #mbox-cells = <1>; + }; + + bpmp@d0000000 { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; + status = "disabled"; + }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-ram"; + reg = <0x0 0x30000000 0x0 0x4ffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x4ffff>; + + cpu_bpmp_tx: bpmp_shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + cpu_bpmp_rx: bpmp_shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; +};