From patchwork Thu Jul 20 00:29:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 791312 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rere.qmqm.pl header.i=@rere.qmqm.pl header.b="pk9xp6CQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xCZXS4L1dz9t2S for ; Thu, 20 Jul 2017 10:29:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754293AbdGTA30 (ORCPT ); Wed, 19 Jul 2017 20:29:26 -0400 Received: from rere.qmqm.pl ([91.227.64.183]:50904 "EHLO rere.qmqm.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753680AbdGTA3Z (ORCPT ); Wed, 19 Jul 2017 20:29:25 -0400 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 877BC329; Thu, 20 Jul 2017 02:29:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1500510564; bh=+iopp8kEV8dyLnlsFfSXrpilBBQjNIVTe2cKHgUa5gQ=; h=Date:In-Reply-To:References:From:Subject:To:From; b=pk9xp6CQ5r86lqZKyspm4XDFuOio1pMd4zO6WPNTb+KEPu9nRADzNQozW4NykYKkE UJ27S+2Cw/nLqrS94iW0LGqXeu1ljmvWBuHGs0yJ8E8qGkJDK0q44oR0L8PWcPPMm3 H+/J4nwIxRssBdSDadO3yTB9wk59k4a7oSyZRlKf6r5Ghe5CLLylo08HCo+bCfcZ+u 0B0DOMEGZlxfwt2rs+cw5BvUJi+Ke1ZpiS/EwgexVXGVn+d5dAA8cAZIw3OT5ecn5h VPV6hqgRDY48otK1V2AXsckRdzqxRJuRtLp6WET+Ii4jpbCXIoDWP01Wz9efG2jm6g mSDLbeCv19r5w== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99.2 at rere Date: Thu, 20 Jul 2017 02:29:24 +0200 Message-Id: <1d12ea86cca40749731a594afc165830c0b2463d.1500510157.git.mirq-linux@rere.qmqm.pl> In-Reply-To: References: From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Subject: [PATCH 4/9] ARM: trusted_foundations: enable L2x0 cache via firmware_ops MIME-Version: 1.0 To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Use firmware_ops to provide hook for cache initialization through Trusted Foundations firmware, as some writes need Secure mode. Signed-off-by: Michał Mirosław --- arch/arm/firmware/trusted_foundations.c | 46 ++++++++++++++++++++++++++++++ arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 10 ++++++- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 3fb1b5a1dce9..81ff71b87438 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -17,11 +17,19 @@ #include #include #include +#include #include +#include +#include #include +#define TF_CACHE_MAINT 0xfffff100 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CACHE_INIT 1 +#define TF_CACHE_FLUSH 2 +#define TF_CACHE_REENABLE 4 + #define TF_CPU_PM 0xfffffffc #define TF_CPU_PM_S3 0xffffffe3 #define TF_CPU_PM_S2 0xffffffe6 @@ -63,9 +71,47 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_write_sec(unsigned long val, unsigned reg) +{ + unsigned long cur = readl_relaxed(l2x0_base + reg); + + pr_warn("TF: ignoring write_sec[0x%x]: 0x%08lx -> 0x%08lx\n", reg, cur, val); +} + +static void tf_disable_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_FLUSH, l2x0_way_mask); +} + +static void tf_resume_cache(void) +{ + unsigned long aux_val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_REENABLE, aux_val); +} + +static void tf_configure_cache(const struct l2x0_regs *regs) +{ + outer_cache.disable = tf_disable_cache; + outer_cache.resume = tf_resume_cache; +} + +static int tf_init_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_INIT, 0); + + outer_cache.write_sec = tf_write_sec; + outer_cache.configure = tf_configure_cache; + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 492de655e4f3..665eb0758417 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -194,6 +194,7 @@ struct l2x0_regs { }; extern void __iomem *l2x0_base; +extern u32 l2x0_way_mask; /* Bitmask of active ways */ extern struct l2x0_regs l2x0_saved_regs; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index bbfbc18399f9..f1268e9b35f0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "cache-tauros3.h" #include "cache-aurora-l2.h" @@ -37,6 +38,7 @@ struct l2c_init_data { const char *type; unsigned way_size_0; unsigned num_lock; + void (*init)(void __iomem *, u32 *, u32 *); void (*of_parse)(const struct device_node *, u32 *, u32 *); void (*enable)(void __iomem *, unsigned); void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); @@ -50,11 +52,11 @@ struct l2c_init_data { static const struct l2c_init_data *l2x0_data; static DEFINE_RAW_SPINLOCK(l2x0_lock); -static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; void __iomem *l2x0_base; +u32 l2x0_way_mask; /* Bitmask of active ways */ struct l2x0_regs l2x0_saved_regs; static bool l2x0_bresp_disable; @@ -1760,6 +1762,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) u32 cache_id; u32 cache_level = 2; bool nosync = false; + int err; np = of_find_matching_node(NULL, l2x0_ids); if (!np) @@ -1792,6 +1795,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) nosync = of_property_read_bool(np, "arm,outer-sync-disable"); + /* Call firmware init */ + err = call_firmware_op(l2x0_init); + if (err && err != -ENOSYS) + return err; + /* Read back current (default) hardware configuration */ if (data->save) data->save(l2x0_base);