@@ -53,17 +53,24 @@ static int tegra210_i2s_set_clock_rate(struct device *dev,
regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val);
- /* No need to set rates if I2S is being operated in slave */
- if (!(val & I2S_CTRL_MASTER_EN))
- return 0;
-
- err = clk_set_rate(i2s->clk_i2s, clock_rate);
- if (err) {
- dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
- clock_rate, err);
- return err;
+ /*
+ * If I2S is consumer, then the clock rate is expected to be
+ * set by the respective provider and thus just read the rate
+ * in such case. If I2S is provider, then set the clock rate.
+ */
+ if (!(val & I2S_CTRL_MASTER_EN)) {
+ clock_rate = clk_get_rate(i2s->clk_i2s);
+ } else {
+ err = clk_set_rate(i2s->clk_i2s, clock_rate);
+ if (err) {
+ dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n",
+ clock_rate, err);
+ return err;
+ }
}
+ dev_dbg(dev, "bit clock (BCLK) rate is %u\n", clock_rate);
+
if (!IS_ERR(i2s->clk_sync_input)) {
/*
* Other I/O modules in AHUB can use i2s bclk as reference
When Tegra I2S is consumer the clock is driven by the external codec. In such cases, ideally the bit clock (BCLK) rate needs to be updated by provider. Consumer can use standard clock function to get the rate. On Tegra HW it is possible to use I2S BCLK clock as reference to the I/O (other I2S or DMIC or DSPK) interfaces. This input clock is called as SYNC input clock and it can act as a parent clock to any of the remaining I/O interfaces. Thus it is important to set the clock rate in Tegra I2S consumer mode as well. With this patch SYNC input clock rate is updated and any I/O interface relying on this can derive required rate. Signed-off-by: Sameer Pujar <spujar@nvidia.com> --- Following are the DT binding cases I tried on Jetson AGX Xavier platform. 1. Sysclk derived from MCLK : This is currently being used. No DT binding change would be necessary. Clock tree dump snippet in this case with proposed series: ... pll_a | |-- plla_out0 | |-- ahub | |-- aud_mclk | | | |-- rt5659_sysclk | |-- i2s1 ... 2. Sysclk is derived from codec internal PLL and this PLL uses I2S bit clock (BCLK) as reference. rt5658: audio-codec@1a { ... clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>, <&bpmp TEGRA194_CLK_I2S1>, <&bpmp TEGRA194_CLK_I2S1>, <&rt5658 0>; clock-names = "mclk", "bclk1", "pll_ref", "sysclk"; #clock-cells = <1>; clock-output-names = "rt5659_pll_out"; ... }; Clock tree dump snippet in this case with proposed series: ... pll_a | |-- plla_out0 | |-- ahub | |-- aud_mclk | |-- i2s1 | |-- rt5659_pll_ref | |-- rt5659_pll_out | |-- rt5659_sysclk ... sound/soc/tegra/tegra210_i2s.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-)