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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2022 10:30:17.4940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fe058a0-2d94-4850-7627-08d9e7c9568d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1252 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra194 and later chips support combined sequence mode which result in less interrupts and better perf. This flag helps enable it. Signed-off-by: Krishna Yarlagadda --- Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 6efea89..3767059 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -46,6 +46,14 @@ properties: - const: rx - const: tx + nvidia,cmb-xfer: + description: + Enable combined sequence transfers for read and program sequence + if supported by hardware. Tegra194 and later chips support this + feature. Default is non combined sequence. SPI message should + contain CMD-ADDR-DATA transfers to combine and send to hardware. + type: boolean + patternProperties: "@[0-9a-f]+": type: object